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# Machinemodel file for M7/T7 systems
#
# Copyright (C) 2021-2024 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
indxobj_define M7_Chip (CPUID>>8)
indxobj_define M7_Core (CPUID>>3)
mobj_define Memory_page_size "(EA_PAGESIZE ? EA_PAGESIZE : -1)"
mobj_define Memory_page "(((VADDR>255) && EA_PAGESIZE) ? VADDR & (~(EA_PAGESIZE-1)) : -1)"
mobj_define Memory_64B_cacheline "((VADDR>255)?(VADDR>>6<<6):-1)"
mobj_define Memory_32B_cacheline "((VADDR>255)?(VADDR>>5<<5):-1)"
mobj_define Memory_address "((VADDR>255)?(VADDR):-1)"
mobj_define Memory_in_home_lgrp (EA_LGRP==LWP_LGRP_HOME)
mobj_define Memory_lgrp (EA_LGRP)
mobj_define Physical_page "((PADDR && EA_PAGESIZE) ? PADDR & (~(EA_PAGESIZE-1)) : -1)"
mobj_define Physical_64B_cacheline "(PADDR?(PADDR>>6<<6):-1)"
mobj_define Physical_32B_cacheline "(PADDR?(PADDR>>5<<5):-1)"
mobj_define Physical_address "(PADDR?(PADDR):-1)"
#mobj_define Vpage_8K "((ea_pagesize==1<<13 && VADDR>255)?(VADDR>>13<<13):-1)"
#mobj_define Vpage_64K "((ea_pagesize==1<<16 && VADDR>255)?(VADDR>>16<<16):-1)"
#mobj_define Vpage_4M "((ea_pagesize==1<<22 && VADDR>255)?(VADDR>>22<<22):-1)"
#mobj_define Vpage_256M "((ea_pagesize==1<<28 && VADDR>255)?(VADDR>>28<<28):-1)"
#mobj_define Vpage_2G "((ea_pagesize==1<<31 && VADDR>255)?(VADDR>>31<<31):-1)"
#mobj_define Vpage_16G "((ea_pagesize==1<<34 && VADDR>255)?(VADDR>>34<<34):-1)"
#mobj_define Ppage_8K "((ea_pagesize==1<<13 && PADDR)?(PADDR>>13<<13):-1)"
#mobj_define Ppage_64K "((ea_pagesize==1<<16 && PADDR)?(PADDR>>16<<16):-1)"
#mobj_define Ppage_4M "((ea_pagesize==1<<22 && PADDR)?(PADDR>>22<<22):-1)"
#mobj_define Ppage_256M "((ea_pagesize==1<<28 && PADDR)?(PADDR>>28<<28):-1)"
#mobj_define Ppage_2G "((ea_pagesize==1<<31 && PADDR)?(PADDR>>31<<31):-1)"
#mobj_define Ppage_16G "((ea_pagesize==1<<34 && PADDR)?(PADDR>>34<<34):-1)"
# we dropped the *CacheTag definitions since:
# - they're rarely used
# - it's unclear if they are correct for S4
# comment out other *Cache* definitions since we don't have use cases to justify their complexity
# further, meminfo() tends not to give us physical addresses
#mobj_define M7_L1ICacheSet "((PHYSPC>>6)&0x3F)"
#mobj_define M7_L1DCacheSet "(PADDR?((PADDR>>5)&0x7F):-1)"
#mobj_define M7_L2ICacheSet "((((PHYSPC&0xFFFFFFFFFFF00FFF)|(((PHYSPC>>24)^(PHYSPC>>16)^(PHYSPC>>8)^PHYSPC)&0xFF000))>>6)&0x1FF)"
#mobj_define M7_L2DCacheSet "(PADDR?((((PADDR&0x2000000000000)?PADDR:((PADDR&0xFFFFFFFFFFF00FFF)|(((PADDR>>24)^(PADDR>>16)^(PADDR>>8)^PADDR)&0xFF000)))>>6)&0x01FF):-1)"
#mobj_define M7_L3DCacheSet "(PADDR?((((PADDR&0x2000000000000)?PADDR:((PADDR&0xFFFFFFFFFFF00FFF)|(((PADDR>>24)^(PADDR>>16)^(PADDR>>8)^PADDR)&0xFF000)))>>6)&0x3FFF):-1)"
#mobj_define M7_L3DBank "(PADDR?((((PADDR&0x2000000000000)?PADDR:((PADDR&0xFFFFFFFFFFF00FFF)|(((PADDR>>24)^(PADDR>>16)^(PADDR>>8)^PADDR)&0xFF000)))>>6)&0x0001):-1)"
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