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* GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker2016-01-01577-577/+577
* sim: m68hc11: fix default endianMike Frysinger2015-12-303-2/+7
* sim: cris/m68hc11: move default endian/alignment to configureMike Frysinger2015-12-308-14/+115
* sim: h8300: inline sim_state_initializeMike Frysinger2015-12-302-27/+7
* sim: h8300: simplify h8300_reg_{fetch,store} funcsMike Frysinger2015-12-302-53/+29
* sim: h8300: switch to common sim-resumeMike Frysinger2015-12-303-40/+57
* sim: h8300: move default endian/alignment to configureMike Frysinger2015-12-304-6/+112
* sim: simplify STATE_MY_NAME setupMike Frysinger2015-12-302-3/+6
* sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to...Mike Frysinger2015-12-3020-86/+169
* sim: h8300: move unused/buggy lregs arrayMike Frysinger2015-12-302-4/+5
* sim: h8300: drop unused inst.hMike Frysinger2015-12-303-104/+5
* sim: ppc: track closed state of file descriptors 0, 1, and 2.Kevin Buettner2015-12-293-22/+151
* sim: aarch64/msp430: fix disassembler usageMike Frysinger2015-12-274-4/+14
* sim: unify sim-hloadMike Frysinger2015-12-2746-67/+93
* sim: punt WITH_DEVICES & tconfig.h supportMike Frysinger2015-12-2695-290/+197
* sim: bfin: push down mmr address/size checksMike Frysinger2015-12-2633-229/+549
* sim: bfin: avoid stack error under asanMike Frysinger2015-12-262-1/+5
* sim: sim-core: pass down cpu to hw accesses when availableMike Frysinger2015-12-262-10/+41
* sim: mips: delete mmu stubs to move to common sim_{read,write}Mike Frysinger2015-12-266-355/+153
* sim: cris: do not pass cpu when writing memory during initMike Frysinger2015-12-262-5/+10
* sim: standardize sim_create_inferior handling of argv a bit moreMike Frysinger2015-12-2618-34/+106
* sim: aarch64: move ChangeLog contentMike Frysinger2015-12-262-26/+25
* sim: frv: punt WITH_DEVICE supportMike Frysinger2015-12-256-95/+10
* sim: m32r: migrate from WITH_DEVICES to WITH_HWMike Frysinger2015-12-2512-178/+361
* sim: cris: migrate from WITH_DEVICES to WITH_HWMike Frysinger2015-12-2510-126/+113
* sim: cris: clean up rvdummy a bitMike Frysinger2015-12-252-2/+6
* sim: cris: set up sane default path to rvdummyMike Frysinger2015-12-252-1/+14
* sim: hw-properties: delete trace callsMike Frysinger2015-12-252-4/+8
* sim: drop WITH_ENGINE defineMike Frysinger2015-12-253-15/+5
* sim: sim-model: build for everyoneMike Frysinger2015-12-2529-49/+75
* sim: move MACH/MODEL types into SIM_xxx namespaceMike Frysinger2015-12-2533-116/+172
* sim: arm: delete unused codeMike Frysinger2015-12-2523-3651/+34
* sim: move WITH_SCACHE_PBB to sim-main.hMike Frysinger2015-12-2518-49/+57
* sim: device_error: puntMike Frysinger2015-12-2512-52/+32
* sim: always enable callback memoryMike Frysinger2015-12-254-13/+13
* sim: dv-pal: always use CPU_INDEXMike Frysinger2015-12-252-5/+7
* sim: mips: delete TARGET_TX3904 defineMike Frysinger2015-12-243-2/+5
* sim: mips: move SIM_QUIET_NAN_NEGATED to sim-main.hMike Frysinger2015-12-243-4/+8
* sim: make LMA loading the default for all targetsMike Frysinger2015-12-2425-42/+72
* sim: cris: move option install to sim_openMike Frysinger2015-12-245-19/+18
* sim: delete old breakpoint codeMike Frysinger2015-12-2411-83/+26
* sim: h8300: move h8300-specific options out of common codeMike Frysinger2015-12-245-34/+69
* sim: enable watchpoint module everywhereMike Frysinger2015-12-2418-35/+37
* sim: delete SIM_HAVE_FLATMEM supportMike Frysinger2015-12-246-54/+13
* sim: delete SIM_HAVE_MEM_SIZEMike Frysinger2015-12-248-28/+16
* sim: delete SIM_HAVE_SIMCACHEMike Frysinger2015-12-246-18/+12
* Fix invalid left shift of negative valueDominik Vogt2015-12-1511-33/+55
* Add support for the MRS instruction to the AArch64 simulator.Nick Clifton2015-12-152-9/+53
* Add support for MSP430 F5 hardware multiply.Nick Clifton2015-12-072-10/+59
* Add an AArch64 simulator to GDB.Nick Clifton2015-11-2423-4/+31400