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* nios2: Remove binutils support for Nios II target.Sandra Loosemore2024-11-263-1790/+0
| | | | | | | | | | The Nios II architecture has been EOL'ed by the vendor. This patch removes all binutils, bfd, gas, binutils, and opcodes support for this target with the exception of the readelf utility. (The ELF EM_* number remains valid and the relocation definitions from the Nios II ABI will never change in future, so retaining the readelf support seems consistent with its purpose as a utility that tries to parse the headers in any ELF file provided as an argument regardless of target.)
* RISC-V: Support SiFive extensions: xsfvqmaccdod, xsfvqmaccqoq and ↵Nelson Chu2024-11-222-0/+25
| | | | | | | | | | | | | | | | | | xsfvfnrclipxfqf Those SiFive extensions have been published on the web for a while, and we plan to implement intrinsics in GCC for those instructions soon. NOTE: The original patch was written by Nelson when he was still working at SiFive, and Kito rebased it to the trunk. Therefore, I kept the author as Nelson with his SiFive email. Document links: xsfvqmaccdod: https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification xsfvqmaccqoq: https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification xsfvfnrclipxfqf: https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
* RISC-V: Add Zcmt instructions and csr.Jiawei2024-11-202-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports Zcmt[1] instruction 'cm.jt' and 'cm.jalt'. Add new CSR jvt for tablejump using. Since 'cm.jt' and 'cm.jalt' have the same instructiong encoding, use 'match_cm_jt' and 'match_cm_jalt' check the 'zcmt_index' field to distinguish them. [1] https://github.com/riscvarchive/riscv-code-size-reduction/releases Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): New CSR. (riscv_csr_address): Ditto. (validate_riscv_insn): New operand. (riscv_ip): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New CSR. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. * testsuite/gas/riscv/zcmt-fail.d: New test. * testsuite/gas/riscv/zcmt-fail.l: New test. * testsuite/gas/riscv/zcmt-fail.s: New test. * testsuite/gas/riscv/zcmt.d: New test. * testsuite/gas/riscv/zcmt.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CM_JT): New opcode. (MASK_CM_JT): New mask. (MATCH_CM_JALT): New opcode. (MASK_CM_JALT): New mask. (CSR_JVT): New CSR. (DECLARE_INSN): New declaration. (DECLARE_CSR): Ditto. * opcode/riscv.h (EXTRACT_ZCMT_INDEX): New marco. (ENCODE_ZCMT_INDEX): Ditto. (enum riscv_insn_class): New class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): New operand. * riscv-opc.c (match_cm_jt): New function. (match_cm_jalt): Ditto.
* aarch64: improve debuggability on array of enumMatthieu Longo2024-11-081-3/+3
| | | | | | | | | | | | The current space optmization on enum aarch64_opn_qualifier forced its encoding using an unsigned char. This "hard-coded" optimization has the bad consequence of making the array of such enums being completely unreadable when debugging with GDB because the enum type is lost along the way. Keeping this space optimization, and the enum type as well, is possible when the declaration of the enum is tagged with attribute((packed)). attribute((packed)) is a GNU extension, and is wrapped in the macro ATTRIBUTE_PACKED (defined in ansidecl.h), and should be used instead.
* aarch64: change returned type to bool to match semantic of functionsMatthieu Longo2024-11-081-1/+1
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* aarch64: make comment clearer about the locationMatthieu Longo2024-11-081-1/+2
| | | | | | | | | The enum aarch64_opnd_qualifiers in include/opcode/aarch64.h needs to stay in sync with the array of struct operand_qualifier_data which defines various properties for the different type of operands. For instance, for: - registers: the size of the register, the number of elements. - immediates: lower and upper bits to determine the range of values.
* arm, objdump: Make objdump use bfd's machine detection to drive disassemblyAndre Vieira2024-11-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For any arm elf target, disable an old piece of code that forced disassembly to disassemble for 'unknown architecture' which once upon a time meant it would disassemble ANY arm instruction. This is no longer true with the addition of Armv8.1-M Mainline, as there are conflicting encodings for different thumb instructions. BFD however can detect what architecture the object file was assembled for using information in the notes section. So if available, we use that, otherwise we default to the old 'unknown' behaviour. With the changes above code, a mode changing 'bx lr' assembled for armv4 with the option --fix-v4bx will result in an object file that is recognized by bfd as one for the armv4 architecture. The disassembler now disassembles this encoding as a BX even for Armv4 architectures, but warns the user when disassembling for Armv4 that this instruction is only valid from Armv4T onwards. Remove the unused and wrongfully defined ARM_ARCH_V8A_CRC, and define and use a ARM_ARCH_V8R_CRC to make sure instructions enabled by -march=armv8-r+crc are disassembled correctly. Patch up some of the tests cases, see a brief explanation for each below. inst.d: This test checks the assembly & disassembly of basic instructions in armv3m. I changed the expected behaviour for teqp, cmnp cmpp and testp instructions to properly print p when disassembling, whereas before, in the 'unknown' case it would disassemble these as UNPREDICTABLE as they were changed in later architectures. nops.d: Was missing an -march, added one to make sure we were testing the right behavior of NOP<c> instructions. unpredictable.d: Was missing an -march, added armv6 as that reproduced the behaviour being tested.
* s390: Add arch15 instructionsAndreas Krebbel2024-10-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | opcodes/ * s390-mkopc.c (main) Accept arch15 as CPU string. * s390-opc.txt: Add arch15 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH15. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch15. * doc/c-s390.texi: Document arch15 march option. * doc/as.texi: Likewise. * testsuite/gas/s390/s390.exp: Run the arch15 related tests. * testsuite/gas/s390/zarch-arch15.d: Tests for arch15 instructions. * testsuite/gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Andreas Krebbel <krebbel@linux.ibm.com> Reviewed-by: Jens Remus <jremus@linux.ibm.com>
* include: de-duplicate i386.h and x86_64.hJan Beulich2024-10-043-67/+61
| | | | | Move common definitions to a new x86.h, thus allowing gas'es obj-coff.h to include just that, getting rid of a TE_PEP compile-time dependency.
* Add support for IMPORT_NAME_EXPORTAS in ILF (MSVC style) import librariesMartin Storsjö2024-10-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | This import name type is formally yet undocumented, but MSVC produces/supports it, primarily for ARM64EC import libraries. LLVM/LLD also supports this import name type. Since recently, llvm-dlltool also uses this type for certain kinds of renamed imports (that are easy to do in the long style import libraries produced by GNU dlltool, but require this name type in short import libraries). This name type contains a third string, in addition to the symbol name and the DLL name, indicating the actual imported name to reference in the import tables - which now can be distinct different from the symbol name on the object file level. https://github.com/llvm/llvm-project/commit/8f23464a5d957242c89ca6f33d4379c42519cd81 and https://github.com/llvm/llvm-project/commit/7b275aa2438c22604505d618dd37ee60052f2800 show how this import name type was added in LLVM. Signed-off-by: Martin Storsjö <martin@martin.st>
* RISC-V: Add Smrnmi extension csrs.Jiawei2024-09-251-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch support Smrnmi extension[1], The csrs address can be find in[2]. [1] https://github.com/riscv/riscv-isa-manual/commit/35eb3948bf0b87c83fab5a7238bd68b6211faf62 [2] https://github.com/riscv/riscv-isa-manual/blob/smrnmi-1.0/src/priv-csrs.adoc bfd/ChangeLog: * elfxx-riscv.c: New extension. gas/ChangeLog: * NEWS: Add Smrnmi extension support. * config/tc-riscv.c (enum riscv_csr_class): New extension class. (riscv_csr_address): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New csrs. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. include/ChangeLog: * opcode/riscv-opc.h (CSR_MNSCRATCH): New csr. (CSR_MNEPC): Ditto. (CSR_MNCAUSE): Ditto. (CSR_MNSTATUS): Ditto. (DECLARE_CSR): New csr declarations.
* MIPS/opcodes: Rework documentation for instruction argsMaciej W. Rozycki2024-09-151-400/+402
| | | | | | Rewrite the inline documentation for the characters used in the `args' member of `struct mips_opcode' to make it consistent in terms of style and formatting. Discard references to inexistent macros.
* s390: Simplify (dis)assembly of insn operands with const bitsJens Remus2024-09-121-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify assembly and disassembly of extended mnemonics with operands with constant ORed bits: Their instruction template already contains the respective constant operand bits, as they are significant to distinguish the extended from their base mnemonic. Operands are ORed into the instruction template. Therefore it is not necessary to OR the constant bits into the operand value during assembly in s390_insert_operand. Additionally the constant operand bits from the instruction template can be used to mask them from the operand value during disassembly in s390_print_insn_with_opcode. For now do so for non-length unsigned integer operands only. The separate instruction formats need to be retained, as their masks differ, which is relevant during disassembly to distinguish the base and extended mnemonics from each other. This affects the following extended mnemonics: - vfaebs, vfaehs, vfaefs - vfaezb, vfaezh, vfaezf - vfaezbs, vfaezhs, vfaezfs - vstrcbs, vstrchs, vstrcfs - vstrczb, vstrczh, vstrczf - vstrczbs, vstrczhs, vstrczfs - wcefb, wcdgb - wcelfb, wcdlgb - wcfeb, wcgdb - wclfeb, wclgdb - wfisb, wfidb, wfixb - wledb, wflrd, wflrx include/ * opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2, S390_OPERAND_OR8): Remove. opcodes/ * s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove. (INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask. (INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining respective insn fmt mask. (INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3): Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt mask. * s390-dis.c (s390_print_insn_with_opcode): Mask constant operand bits set in insn template of non-length unsigned integer operands. gas/ * config/tc-s390.c (s390_insert_operand): Do not OR constant operand value bits. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
* Add macros to get opcode of instructions approriatelyXin Wang2024-09-071-5/+65
| | | | | | | | | LoongArch: Add macros to get opcode and register of instructions appropriately Currently, we get opcode of an instruction by manipulate the binary with it's mask, it's a bit of a pain. Now a macro is defined to do this and a macro to get the RD and RJ registers which is applicable to most instructions of LoongArch are added.
* RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett2024-09-032-0/+452
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvsimd` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): Add custom operands. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVsimd as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvsimd. * testsuite/gas/riscv/x-cv-simd.d: New test. * testsuite/gas/riscv/x-cv-simd.s: New test. * testsuite/gas/riscv/x-cv-simd-fail.d: New test. * testsuite/gas/riscv/x-cv-simd-fail.l: New test. * testsuite/gas/riscv/x-cv-simd-fail.s: New test. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVsimd. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVsimd. (enum riscv_insn_class): Add the XCVsimd instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands. * riscv-opc.c: Add XCVsimd instructions.
* RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.Jiawei2024-08-272-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'. All disassemble instructions use the sreg format. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> gas/ChangeLog: PR 32036 * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcmp-mv.d: New test. * testsuite/gas/riscv/zcmp-mv.s: New test. include/ChangeLog: PR 32036 * opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode. (MASK_CM_MVA01S): New mask. (MATCH_CM_MVSA01): New opcode. (MASK_CM_MVSA01): New mask. (DECLARE_INSN): New declarations. * opcode/riscv.h (OP_MASK_SREG1): New mask. (OP_SH_SREG1): New operand code. (OP_MASK_SREG2): New mask. (OP_SH_SREG2): New operand code. (X_A0): New reg number. (X_A1): Ditto. (X_S7): Ditto. (RISCV_SREG_0_7): New macro function. opcodes/ChangeLog: PR 32036 * riscv-dis.c (riscv_zcmp_get_sregno): New function. (print_insn_args): New operators. * riscv-opc.c (match_sreg1_not_eq_sreg2): New match function.
* RISC-V: Add support for XCvBitmanip extension in CV32E40PMary Bennett2024-08-062-2/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvbitmanip` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add custom operands `Xc6` and `Xc7`. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbitmanip as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvbitmanip. * testsuite/gas/riscv/x-cv-bitmanip-fail.d: New Test. * testsuite/gas/riscv/x-cv-bitmanip-fail.l: New Test. * testsuite/gas/riscv/x-cv-bitmanip-fail.s: New Test. * testsuite/gas/riscv/x-cv-bitmanip.d: New Test. * testsuite/gas/riscv/x-cv-bitmanip.s: New Test. include/opcode/ChangeLog: * riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbitmanip. * riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbitmanip. (enum riscv_insn_class): Add the XCVbitmanip instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands `Xc6` and `Xc7`. * riscv-opc.c: Add XCvBitmanip instructions.
* RISC-V: Add support for Zcmop extensionXiao Zeng2024-08-062-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements the Zcmop (Compressed Zimop) extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc> The Zcmop extension requires the Zca extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zcmop. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zcmop.d: New test. * testsuite/gas/riscv/zcmop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (DECLARE_INSN): New declarations for Zcmop. (MATCH_C_MOP_1, MATCH_C_MOP_3, MATCH_C_MOP_5, MATCH_C_MOP_7, MATCH_C_MOP_9, MATCH_C_MOP_11, MATCH_C_MOP_13, MATCH_C_MOP_15): Define. (MASK_C_MOP_1, MASK_C_MOP_3, MASK_C_MOP_5, MASK_C_MOP_7, MASK_C_MOP_9, MASK_C_MOP_11, MASK_C_MOP_13, MASK_C_MOP_15): Ditto. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZCMOP. opcodes/ChangeLog: * riscv-opc.c: Add Zcmop instructions.
* RISC-V: Add support for Zimop extensionXiao Zeng2024-08-062-0/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements the Zimop (May-Be-Operations) extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zimop (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zimop.d: New test. * testsuite/gas/riscv/zimop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (DECLARE_INSN): New declarations for Zimop. (MATCH_MOP_R_0, MATCH_MOP_R_1, MATCH_MOP_R_2, MATCH_MOP_R_3, MATCH_MOP_R_4, MATCH_MOP_R_5, MATCH_MOP_R_6, MATCH_MOP_R_7, MATCH_MOP_R_8, MATCH_MOP_R_9, MATCH_MOP_R_10, MATCH_MOP_R_11, MATCH_MOP_R_12, MATCH_MOP_R_13, MATCH_MOP_R_14, MATCH_MOP_R_15, MATCH_MOP_R_16, MATCH_MOP_R_17, MATCH_MOP_R_18, MATCH_MOP_R_19, MATCH_MOP_R_20, MATCH_MOP_R_21, MATCH_MOP_R_22, MATCH_MOP_R_23, MATCH_MOP_R_24, MATCH_MOP_R_25, MATCH_MOP_R_26, MATCH_MOP_R_27, MATCH_MOP_R_28, MATCH_MOP_R_29, MATCH_MOP_R_30, MATCH_MOP_R_31, MATCH_MOP_RR_0, MATCH_MOP_RR_1, MATCH_MOP_RR_2, MATCH_MOP_RR_3, MATCH_MOP_RR_4, MATCH_MOP_RR_5, MATCH_MOP_RR_6, MATCH_MOP_RR_7): Define. (MASK_MOP_R_0, MASK_MOP_R_1, MASK_MOP_R_2, MASK_MOP_R_3, MASK_MOP_R_4, MASK_MOP_R_5, MASK_MOP_R_6, MASK_MOP_R_7, MASK_MOP_R_8, MASK_MOP_R_9, MASK_MOP_R_10, MASK_MOP_R_11, MASK_MOP_R_12, MASK_MOP_R_13, MASK_MOP_R_14, MASK_MOP_R_15, MASK_MOP_R_16, MASK_MOP_R_17, MASK_MOP_R_18, MASK_MOP_R_19, MASK_MOP_R_20, MASK_MOP_R_21, MASK_MOP_R_22, MASK_MOP_R_23, MASK_MOP_R_24, MASK_MOP_R_25, MASK_MOP_R_26, MASK_MOP_R_27, MASK_MOP_R_28, MASK_MOP_R_29, MASK_MOP_R_30, MASK_MOP_R_31, MASK_MOP_RR_0, MASK_MOP_RR_1, MASK_MOP_RR_2, MASK_MOP_RR_3, MASK_MOP_RR_4, MASK_MOP_RR_5, MASK_MOP_RR_6, MASK_MOP_RR_7): Ditto. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZIMOP. opcodes/ChangeLog: * riscv-opc.c: Add Zimop instructions.
* libctf, include: add ctf_dict_set_flag: less enum dup checking by defaultNick Alcock2024-07-311-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The recent change to detect duplicate enum values and return ECTF_DUPLICATE when found turns out to perturb a great many callers. In particular, the pahole-created kernel BTF has the same problem we historically did, and gleefully emits duplicated enum constants in profusion. Handling the resulting duplicate errors from BTF -> CTF converters reasonably is unreasonably difficult (it amounts to forcing them to skip some types or reimplement the deduplicator). So let's step back a bit. What we care about mostly is that the deduplicator treat enums with conflicting enumeration constants as conflicting types: programs that want to look up enumeration constant -> value mappings using the new APIs to do so might well want the same checks to apply to any ctf_add_* operations they carry out (and since they're *using* the new APIs, added at the same time as this restriction was imposed, there is likely to be no negative consequence of this). So we want some way to allow processes that know about duplicate detection to opt into it, while allowing everyone else to stay clear of it: but we want ctf_link to get this behaviour even if its caller has opted out. So add a new concept to the API: dict-wide CTF flags, set via ctf_dict_set_flag, obtained via ctf_dict_get_flag. They are not bitflags but simple arbitrary integers and an on/off value, stored in an unspecified manner (the one current flag, we translate into an LCTF_* flag value in the internal ctf_dict ctf_flags word). If you pass in an invalid flag or value you get a new ECTF_BADFLAG error, so the caller can easily tell whether flags added in future are valid with a particular libctf or not. We check this flag in ctf_add_enumerator, and set it around the link (including on child per-CU dicts). The newish enumerator-iteration test is souped up to check the semantics of the flag as well. The fact that the flag can be set and unset at any time has curious consequences. You can unset the flag, insert a pile of duplicates, then set it and expect the new duplicates to be detected, not only by ctf_add_enumerator but also by ctf_lookup_enumerator. This means we now have to maintain the ctf_names and conflicting_enums enum-duplication tracking as new enums are added, not purely as the dict is opened. Move that code out of init_static_types_internal and into a new ctf_track_enumerator function that addition can also call. (None of this affects the file format or serialization machinery, which has to be able to handle duplicate enumeration constants no matter what.) include/ * ctf-api.h (CTF_ERRORS) [ECTF_BADFLAG]: New. (ECTF_NERR): Update. (CTF_STRICT_NO_DUP_ENUMERATORS): New flag. (ctf_dict_set_flag): New function. (ctf_dict_get_flag): Likewise. libctf/ * ctf-impl.h (LCTF_STRICT_NO_DUP_ENUMERATORS): New flag. (ctf_track_enumerator): Declare. * ctf-dedup.c (ctf_dedup_emit_type): Set it. * ctf-link.c (ctf_create_per_cu): Likewise. (ctf_link_deduplicating_per_cu): Likewise. (ctf_link): Likewise. (ctf_link_write): Likewise. * ctf-subr.c (ctf_dict_set_flag): New function. (ctf_dict_get_flag): New function. * ctf-open.c (init_static_types_internal): Move enum tracking to... * ctf-create.c (ctf_track_enumerator): ... this new function. (ctf_add_enumerator): Call it. * libctf.ver: Add the new functions. * testsuite/libctf-lookup/enumerator-iteration.c: Test them.
* include, libctf: improve ECTF_DUPLICATE error messageNick Alcock2024-07-311-1/+1
| | | | | | | It applies to enums now, so it should mention them. include/ * ctf-api.h (_CTF_ERRORS) ECTF_DUPLICATE]: Mention enums.
* libctf: improve ECTF_NOPARENT error messageNick Alcock2024-07-311-1/+1
| | | | | | | | | | | | This erorr doesn't just indicate that there is no parent dictionary (that's routine, and true of all dicts that are parents themselves) but that a parent is *needed* but wasn't found. include/ * ctf-api.h (_CTF_ERRORS) [ECTF_NOPARENT]: Improve error message. ld/ * testsuite/ld-ctf/diag-parname.d: Adjust.
* microMIPS: Add MT ASE instruction set supportYunQiang Su2024-07-261-3/+11
| | | | | | | | | | | | | | Add the MT ASE instruction operand types and encodings to the microMIPS opcode table and enable the assembly of these instructions in GAS from MIPSr2 onwards. Update the binutils and GAS testsuites accordingly. References: "MIPS Architecture for Programmers, Volume IV-f: The MIPS MT Module for the microMIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00768, Revision 1.12, July 16, 2013 Co-Authored-By: Maciej W. Rozycki <macro@redhat.com>
* Improve objdump's display of PE header information.Pali Roh?r2024-07-232-3/+3
| | | | PR 31953
* Add markers for 2.43 branch/releaseNick Clifton2024-07-201-0/+4
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* MIPS/opcodes: Replace "y" microMIPS operand code with "x"Maciej W. Rozycki2024-07-191-2/+2
| | | | | Replace the "y" microMIPS operand code, used with ALNV.PS only, with "x" so as to make "y" available for microMIPS MT use.
* MIPS/opcodes: Remove the regular MIPS "+t" operand codeYunQiang Su2024-07-191-2/+1
| | | | | | | | The semantics of the regular MIPS "+t" operand code is exactly the same as that of the "E" operand code, so replace the former with the latter in the single MFTC0 instruction with implicit 'sel' == 0 encoding where it's used, matching the encoding with explicit 'sel' as well as other instructions.
* MIPS/opcodes: Discard unused OP_SH, OP_MASK, and OP_OP macrosMaciej W. Rozycki2024-07-191-454/+0
| | | | | | | | | | | | | | | | | | | | | As from commit ab90248154ba ("Add structures to describe MIPS operands"), <https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the use of numerous regular MIPS and microMIPS OP_SH and OP_MASK macros has been removed. Similarly as from commit c3c0747817f4 ("Use operand structures for MIPS16"), <https://sourceware.org/ml/binutils/2013-07/msg00136.html>, the use of numerous MIPS16 OP_SH and OP_MASK macros has been removed. And as from commit 9e12b7a2b022 ("Rewrite main mips_ip parsing loop"), <https://sourceware.org/ml/binutils/2013-07/msg00139.html>, none of the OP_OP macros are used anymore. Discard all the unused macros then and only keep the small subset that is still referred. This simplifies maintenance and removes the need to keep the artificial arrangement where some regular MIPS and microMIPS macros expand to 0 and are kept for compatibility with the opposite ISA mode only, as it used to be required before the commit referred.
* MIPS/opcodes: Correct documentation for R6 operand typesMaciej W. Rozycki2024-07-191-7/+6
| | | | | | | | | | The "-t", "-u", "-v", and "-w" operand types refer 'rt' operand, which is the target register rather than the source register. Additionally the "-x" and "-y" R6 operand types refer 'rs' rather than 'rt' operand of the BOVC/BNVC and the BEQC/BNEC instructions respectively. Also the "-x" operand type does not permit 'rs' to be the same as 'rt'. Correct inline documentation in opcode/mips.h accordingly.
* opcodes: aarch64: enforce checks on subclass flags in aarch64-gen.cIndu Bhagat2024-07-181-1/+2
| | | | | | | | | | | | | | | Enforce some checks on the newly added subclass flags: - If a subclass is set of one insn of an iclass, every insn of that iclass must have non-zero subclass field. - For all other iclasses, the subclass bits are zero for all insns. include/ * opcode/aarch64.h (enum aarch64_insn_class): Identify the maximum iclass enum value. opcodes/ * aarch64-gen.c (iclass_has_subclasses_p): New array of bool. (read_table): Enforce checks on subclass flags.
* include: opcodes: aarch64: define new subclassesIndu Bhagat2024-07-181-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing iclass information tells us the general shape and purpose of the instructions. In some cases, however, we need to further disect the iclass on the basis of other finer-grain information. E.g., for the purpose of SCFI, we need to know whether a given insn with iclass of ldst_* is a load or a store. Similarly, whether a particular arithmetic insn is an add or sub or mov, etc. This patch defines new flags to demarcate the insns. Also provide an access function for subclass lookup. Later, we will enforce (in aarch64-gen.c) that if an iclass has at least one instruction with a non-zero subclass, all instructions of the iclass must have a non-zero subclass information. If none of the defined subclasses are applicable (or not required for SCFI purposes), F_SUBCLASS_OTHER can be used for such instructions. include/ * opcode/aarch64.h (F_SUBCLASS): New flag. (F_SUBCLASS_OTHER): Likewise. (F_LDST_LOAD): Likewise. (F_LDST_STORE): Likewise. (F_ARITH_ADD): Likewise. (F_ARITH_SUB): Likewise. (F_ARITH_MOV): Likewise. (F_BRANCH_CALL): Likewise. (F_BRANCH_RET): Likewise. (F_DP_TAG_ONLY): Likewise. (aarch64_opcode_subclass_p): New definition.
* aarch64: Add support for sme2.1 zero instructions.Srinath Parvathaneni2024-07-121-1/+10
| | | | | | | | | | | | | | | | | | This patch adds support for following sme2.1 zero instructions and the spec is available here [1]. 1. ZERO (single-vector). 2. ZERO (double-vector). 3. ZERO (quad-vector). The VECTOR GROUP symbols VGx2 and VGx4 are optional for the assembler for most of the sme and sve instructions. But for few of the sme2.1 zero instruction variants VECTOR GROUP symbols VGx2 and VGx4 are mandatory. To address this a bit "F_VG_REQ" is introduced in this patch, on setting F_VG_REQ bit in flags of aarch64_opcode forces the assembler to accept instruction operand only having VECTOR GROUP symbols. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
* aarch64: Add support for sme2.1 movaz instructions.Srinath Parvathaneni2024-07-121-0/+1
| | | | | | | | | | | This patch adds support for following sme2.1 movaz instructions and the spec is available here [1]. 1. MOVAZ (array to vector, two registers). 2. MOVAZ (array to vector, four registers). 3. MOVAZ (tile to vector, single). [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
* aarch64: Add support for sme2.1 luti2 and luti4 instructions.Srinath Parvathaneni2024-07-121-0/+1
| | | | | | | | | | | | This patch adds support for following sme2.1 luti2 and luti4 instructions, spec is available here [1] 1. LUTI2 (two registers) strided. 2. LUTI2 (four registers) strided. 3. LUTI4 (two registers) strided. 4. LUTI4 (four registers) strided. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
* include: sframe: update code comments around SFrame FRE stack offsetsIndu Bhagat2024-07-091-10/+12
| | | | | | | | | | | | | | | | | | This also amends the incorrect comment: offset3 (intrepreted as FP = CFA + offset2) If RA tracking is enabled, the offset to recover FP is at the third index. The SFrame format (V2) has assumption that if FP is saved on stack, RA must have been saved as well. This is true for the currently supported arch Aarch64. For AMD64, RA tracking per SFrame FRE is not necessary. In future, when extending support for more architectures, this will likely need to be revisited. include/ * sframe.h: Make the comments clearer by enumerating what happens per-ABI.
* LTO: Properly check wrapper symbolH.J. Lu2024-07-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add wrapper_symbol to bfd_link_hash_entry and set it to true for wrapper symbol. Set wrap_status to wrapper if wrapper_symbol is true in LTO. Note: Calling unwrap_hash_lookup to check for the wrapper symbol works only when there is a definition for the wrapped symbol since references to the wrapped symbol have been redirected to the wrapper symbol. bfd/ PR ld/31956 * linker.c (bfd_wrapped_link_hash_lookup): Set wrapper_symbol for wrapper symbol. include/ PR ld/31956 * bfdlink.h (bfd_link_hash_entry): Add wrapper_symbol. ld/ PR ld/31956 * plugin.c (get_symbols): Set wrap_status to wrapper if wrapper_symbol is set. * testsuite/ld-plugin/lto.exp: Run PR ld/31956 tests. * testsuite/ld-plugin/pr31956a.c: New file. * testsuite/ld-plugin/pr31956b.c: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
* aarch64: Add support for sve2p1 pmov instruction.srinath2024-07-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for followign SVE2p1 instruction, spec is available here [1]. 1. PMOV (to vector) 2. PMOV (to predicate) Both pmov (to vector) and pmov (to predicate) have destination scalable vector register and source scalable vector register respectively as an operand with no suffix and optional index. To handle this case we have added 8 new operands in this patch. AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */ AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */ AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */ AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */ AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */ AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */ AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */ AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */ Since the index of the <Zd> operand is optional, the index part is dropped in disassembly in both the cases of "no index" or "zero index". As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D PMOV <Pn>.D, <Zd>{[<imm>]} Example1: Assembly: pmov z5[0], p6.d Disassembly: pmov z5, p6.d Assembly: pmov z5, p6.d Disassembly: pmov z5, p6.d Example2: Assembly: pmov p4.b, z5[0] Disassembly: pmov p4.b, z5 Assembly: pmov p4.b, z5 Disassembly: pmov p4.b, z5 [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
* aarch64: add STEP2 feature and its associated registersMatthieu Longo2024-07-051-0/+3
| | | | | | | | AArch64 defines new registers for the feature step2 (Enhanced Software Step Extension). step2 is an Armv9.5-A feature. This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
* aarch64: add SPMU2 feature and its associated registersMatthieu Longo2024-07-051-0/+3
| | | | | | | | AArch64 defines new registers for the feature spmu2 (System Performance Monitors Extension version 2). spmu2 is an Armv9.5-A feature. This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
* aarch64: add E3DSE feature and its associated registersMatthieu Longo2024-07-051-1/+5
| | | | | | | | | AArch64 defines new registers for the feature e3dse (Delegated SError exceptions for EL3): vdisr_el3 and vdisr_el3. e3dse is an Armv9.5-A feature. This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
* aarch64: Add support for Armv9.5-A architectureClaudio Bantaloukas2024-06-281-0/+8
| | | | | | | The new -march=armv9.5-a flag enables access to the mandatory cpa, lut and faminmax extensions. Existing test cases for features are extended to verify they work without additional flags.
* RISC-V: Add Zabha extension CAS instructions.Jiawei2024-06-282-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch update the cas instruction in Zabha extension [1], when both Zabha and Zacas extension enabled. [1] https://github.com/riscv/riscv-zabha/tags bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension case. gas/ChangeLog: * testsuite/gas/riscv/zabha-32.d: New instructions. * testsuite/gas/riscv/zabha.d: Ditto. * testsuite/gas/riscv/zabha.s: Ditto. include/ChangeLog: * opcode/riscv-opc.h (MATCH_AMOCAS_B): New opcodes. (MASK_AMOCAS_B): Ditto. (MATCH_AMOCAS_H): Ditto. (MASK_AMOCAS_H): Ditto. (DECLARE_INSN): New instructions. * opcode/riscv.h (enum riscv_insn_class): New class case. opcodes/ChangeLog: * riscv-opc.c: New instructions.
* aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.Srinath Parvathaneni2024-06-251-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes encoding and syntax for sve2p1 instructions ld[1-4]q/st[1-4]q as mentioned below, for the issues reported here. https://sourceware.org/pipermail/binutils/2024-February/132408.html 1) Previously all the ld[1-4]q/st[1-4]q instructions are wrongly added as predicated instructions and this issue is fixed in this patch by replacing "SVE2p1_INSNC" with "SVE2p1_INSN" macro. 2) Wrong first operand in all the ld[1-4]q/st[1-4]q instructions is fixed by replacing "SVE_Zt" with "SVE_ZtxN". 3) Wrong operand qualifiers in ld1q and st1q instructions are also fixed in this patch. 4) In ld1q/st1q the index in the second argument is optional and if index is xzr and is skipped in the assembly, the index field is ignored by the disassembler. Fixing above mentioned issues helps with following: 1) ld1q and st1q first register operand accepts enclosed figure braces. 2) ld2q, ld3q, ld4q, st2q, st3q, and st4q instructions accepts wrapping sequence of vector registers. For the instructions ld[2-4]q/st[2-4]q, tests for wrapping sequence of vector registers are added along with short-form of operands for non-wrapping sequence. I have added test using following logic: ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL] //raw insn encoding (all zeroes) ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, #0, MUL VL] // encoding of <Zt1> ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, #0, MUL VL] // encoding of <Pg> ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, #0, MUL VL] // encoding of <Xm> ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #-16, MUL VL] // encoding of <imm> (low value) ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #14, MUL VL] // encoding of <imm> (high value) ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, #-16, MUL VL] // encoding of all fields (all ones) ld2q {Z30.Q, Z31.Q}, p1/Z, [x3, #-2, MUL VL] // random encoding. For all the above form of instructions the hyphenated form is preferred for disassembly if there are more than two registers in the list, and the register numbers are monotonically increasing in increments of one.
* aarch64: Fix sve2p1 extq instruction operands.Srinath Parvathaneni2024-06-251-1/+1
| | | | | | | | | | | | This patch fixes the syntax of sve2p1 "extq" instruction by modifying the operands count to 4. A new operand AARCH64_OPND_SVE_UIMM4 is defined to handle the 4th argument an 4-bit unsigned immediate of extq instruction. The instruction encoding is updated to use constraint C_SCAN_MOVPRFX, to enable "extq" instruction to immediately precede in program order by a MOVPRFX instruction. Also removed the unused operand AARCH64_OPND_SVE_Zm_imm4. This issues was reported here: https://sourceware.org/pipermail/binutils/2024-February/132408.html
* aarch64: Fix sve2p1 dupq instruction operands.Srinath Parvathaneni2024-06-251-1/+1
| | | | | | | | | | | | This patch fixes the syntax of sve2p1 "dupq" instruction by modifying the way 2nd operand does the encoding and decoding using the [<imm>] value. dupq makes use of already existing aarch64_ins_sve_index and aarch64_ext_sve_index inserter and extractor functions. The definitions of aarch64_ins_sve_index_imm (inserter) and aarch64_ext_sve_index_imm (extractor) is removed in this patch. This issues was reported here: https://sourceware.org/pipermail/binutils/2024-February/132408.html
* aarch64: Enable mandatory feature bits for v9.4-A.Srinath Parvathaneni2024-06-251-1/+2
| | | | | This patch fixes the mandatory feature bits in v9.4-a architectures, by enabling FEAT_SVE2p1 for Armv9.4-A architecture by default.
* gdb: LoongArch: Add support for hardware breakpointHui Li2024-06-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LoongArch defines hardware watchpoint functions for fetch operations. After the software configures the watchpoints for fetch, the processor hardware will monitor the access addresses of the fetch operations and trigger a watchpoint exception when the watchpoint setting conditions are met. Hardware watchpoints for fetch operations is used to implement hardware breakpoint function on LoongArch. Refer to the following document for hardware breakpoint. https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#control-and-status-registers-related-to-watchpoints A simple test is as follows: lihui@bogon:~$ cat test.c #include <stdio.h> int a = 0; int main() { printf("start test\n"); a = 1; printf("a = %d\n", a); printf("end test\n"); return 0; } lihui@bogon:~$ gcc -g test.c -o test without this patch: lihui@bogon:~$ gdb test ... (gdb) start ... Temporary breakpoint 1, main () at test.c:5 5 printf("start test\n"); (gdb) hbreak 8 No hardware breakpoint support in the target. with this patch: lihui@bogon:~$ gdb test ... (gdb) start ... Temporary breakpoint 1, main () at test.c:5 5 printf("start test\n"); (gdb) hbreak 8 Hardware assisted breakpoint 2 at 0x1200006ec: file test.c, line 8. (gdb) c Continuing. start test a = 1 Breakpoint 2, main () at test.c:8 8 printf("end test\n"); (gdb) c Continuing. end test [Inferior 1 (process 25378) exited normally] Signed-off-by: Hui Li <lihui@loongson.cn> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
* gdb: LoongArch: Add support for hardware watchpointHui Li2024-06-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LoongArch defines hardware watchpoint functions for load/store operations. After the software configures the watchpoints for load/store, the processor hardware will monitor the access addresses of the load/store operations and trigger watchpoint exception when the watchpoint setting conditions are met. After this patch, watch/rwatch/awatch command are supported. Refer to the following document for hardware watchpoint. https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#control-and-status-registers-related-to-watchpoints A simple test is as follows: lihui@bogon:~$ cat test.c #include <stdio.h> int a = 0; int main() { printf("start test\n"); a = 1; printf("a = %d\n", a); printf("end test\n"); return 0; } lihui@bogon:~$ gcc -g test.c -o test without this patch: lihui@bogon:~$ gdb test ... (gdb) start ... Temporary breakpoint 1, main () at test.c:5 5 printf("start test\n"); (gdb) awatch a Target does not support this type of hardware watchpoint. ... with this patch: lihui@bogon:~$ gdb test ... (gdb) start ... Temporary breakpoint 1, main () at test.c:5 5 printf("start test\n"); (gdb) awatch a Hardware access (read/write) watchpoint 2: a (gdb) c Continuing. start test Hardware access (read/write) watchpoint 2: a Old value = 0 New value = 1 main () at test.c:7 7 printf("a = %d\n", a); (gdb) c Continuing. Hardware access (read/write) watchpoint 2: a Value = 1 0x00000001200006e0 in main () at test.c:7 7 printf("a = %d\n", a); (gdb) c Continuing. a = 1 end test [Inferior 1 (process 22250) exited normally] Signed-off-by: Hui Li <lihui@loongson.cn> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
* aarch64: Add SME FP8 multiplication instructionsAndrew Carlotti2024-06-241-0/+11
| | | | | | | | | | | This includes: - FEAT_SME_F8F32 (+sme-f8f32) - FEAT_SME_F8F16 (+sme-f8f16) The FP16 addition/subtraction instructions originally added by FEAT_SME_F16F16 haven't been added to Binutils yet. They are also required to be enabled if FEAT_SME_F8F16 is present, so they are included in this patch.
* aarch64: Add FP8 Neon and SVE multiplication instructionsAndrew Carlotti2024-06-241-6/+31
| | | | | | | | | | This includes all the instructions under the following features: - FEAT_FP8FMA (+fp8fma) - FEAT_FP8DOT4 (+fp8dot4) - FEAT_FP8DOT2 (+fp8dot2) - FEAT_SSVE_FP8FMA (+ssve-fp8fma) - FEAT_SSVE_FP8DOT4 (+ssve-fp8dot4) - FEAT_SSVE_FP8DOT2 (+ssve-fp8dot2)