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* s390: Add arch15 instructionsAndreas Krebbel2024-10-101-0/+1
* include: de-duplicate i386.h and x86_64.hJan Beulich2024-10-043-67/+61
* Add support for IMPORT_NAME_EXPORTAS in ILF (MSVC style) import librariesMartin Storsjö2024-10-021-0/+1
* RISC-V: Add Smrnmi extension csrs.Jiawei2024-09-251-0/+10
* MIPS/opcodes: Rework documentation for instruction argsMaciej W. Rozycki2024-09-151-400/+402
* s390: Simplify (dis)assembly of insn operands with const bitsJens Remus2024-09-121-4/+0
* Add macros to get opcode of instructions approriatelyXin Wang2024-09-071-5/+65
* RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett2024-09-032-0/+452
* RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.Jiawei2024-08-272-0/+18
* RISC-V: Add support for XCvBitmanip extension in CV32E40PMary Bennett2024-08-062-2/+44
* RISC-V: Add support for Zcmop extensionXiao Zeng2024-08-062-0/+27
* RISC-V: Add support for Zimop extensionXiao Zeng2024-08-062-0/+123
* libctf, include: add ctf_dict_set_flag: less enum dup checking by defaultNick Alcock2024-07-311-2/+14
* include, libctf: improve ECTF_DUPLICATE error messageNick Alcock2024-07-311-1/+1
* libctf: improve ECTF_NOPARENT error messageNick Alcock2024-07-311-1/+1
* microMIPS: Add MT ASE instruction set supportYunQiang Su2024-07-261-3/+11
* Improve objdump's display of PE header information.Pali Roh?r2024-07-232-3/+3
* Add markers for 2.43 branch/releaseNick Clifton2024-07-201-0/+4
* MIPS/opcodes: Replace "y" microMIPS operand code with "x"Maciej W. Rozycki2024-07-191-2/+2
* MIPS/opcodes: Remove the regular MIPS "+t" operand codeYunQiang Su2024-07-191-2/+1
* MIPS/opcodes: Discard unused OP_SH, OP_MASK, and OP_OP macrosMaciej W. Rozycki2024-07-191-454/+0
* MIPS/opcodes: Correct documentation for R6 operand typesMaciej W. Rozycki2024-07-191-7/+6
* opcodes: aarch64: enforce checks on subclass flags in aarch64-gen.cIndu Bhagat2024-07-181-1/+2
* include: opcodes: aarch64: define new subclassesIndu Bhagat2024-07-181-1/+31
* aarch64: Add support for sme2.1 zero instructions.Srinath Parvathaneni2024-07-121-1/+10
* aarch64: Add support for sme2.1 movaz instructions.Srinath Parvathaneni2024-07-121-0/+1
* aarch64: Add support for sme2.1 luti2 and luti4 instructions.Srinath Parvathaneni2024-07-121-0/+1
* include: sframe: update code comments around SFrame FRE stack offsetsIndu Bhagat2024-07-091-10/+12
* LTO: Properly check wrapper symbolH.J. Lu2024-07-091-0/+3
* aarch64: Add support for sve2p1 pmov instruction.srinath2024-07-081-0/+8
* aarch64: add STEP2 feature and its associated registersMatthieu Longo2024-07-051-0/+3
* aarch64: add SPMU2 feature and its associated registersMatthieu Longo2024-07-051-0/+3
* aarch64: add E3DSE feature and its associated registersMatthieu Longo2024-07-051-1/+5
* aarch64: Add support for Armv9.5-A architectureClaudio Bantaloukas2024-06-281-0/+8
* RISC-V: Add Zabha extension CAS instructions.Jiawei2024-06-282-0/+7
* aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.Srinath Parvathaneni2024-06-251-3/+1
* aarch64: Fix sve2p1 extq instruction operands.Srinath Parvathaneni2024-06-251-1/+1
* aarch64: Fix sve2p1 dupq instruction operands.Srinath Parvathaneni2024-06-251-1/+1
* aarch64: Enable mandatory feature bits for v9.4-A.Srinath Parvathaneni2024-06-251-1/+2
* gdb: LoongArch: Add support for hardware breakpointHui Li2024-06-251-0/+2
* gdb: LoongArch: Add support for hardware watchpointHui Li2024-06-251-0/+2
* aarch64: Add SME FP8 multiplication instructionsAndrew Carlotti2024-06-241-0/+11
* aarch64: Add FP8 Neon and SVE multiplication instructionsAndrew Carlotti2024-06-241-6/+31
* gas, aarch64: Add SME2 lutv2 extensionsaurabh.jha@arm.com2024-06-241-0/+6
* aarch64: Enable +cssc for armv8.9-aAndrew Carlotti2024-06-231-0/+1
* libctf, include: new functions for looking up enumeratorsNick Alcock2024-06-181-0/+38
* include: libctf: comment improvementsNick Alcock2024-06-181-2/+5
* libctf: prohibit addition of enums with overlapping enumerator constantsNick Alcock2024-06-181-6/+7
* include: fix libctf ECTF_NOENUMNAM error messageNick Alcock2024-06-181-1/+1
* RISC-V: Add SiFive cease extension v1.0Hau Hsu2024-06-182-0/+4