diff options
| author |   Alan Modra <amodra@gmail.com> | 2006-10-24 01:27:29 +0000 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2006-10-24 01:27:29 +0000 |
| commit | ede602d7c88efaaccf5c0679e0382298ae989d95 (patch) | |
| tree | bc7447faf2f165356db03bf1034546388d2cf999 /opcodes | |
| parent | *** empty log message *** (diff) | |
| download | binutils-gdb-ede602d7c88efaaccf5c0679e0382298ae989d95.tar.gz binutils-gdb-ede602d7c88efaaccf5c0679e0382298ae989d95.tar.bz2 binutils-gdb-ede602d7c88efaaccf5c0679e0382298ae989d95.zip | |
Add powerpc cell support.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 8 | ||||
| -rw-r--r-- | opcodes/ppc-dis.c | 4 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 19 |
3 files changed, 29 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 3173ec31180..7f17d757d43 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> + + * ppc-opc.c (CELL): New define. + (powerpc_opcodes): Enable hrfid for Cell. Add ldbrx and stdbrx, + cell specific instructions. Add {st,l}x{r,l}{,l} cell specific + VMX instructions. + * ppc-dis.c (powerpc_dialect): Handle cell. + 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * i386-dis.c (dis386): Add support for the change in POPCNT opcode in diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index 8b3996a1476..d144892fe2d 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -74,6 +74,10 @@ powerpc_dialect (struct disassemble_info *info) dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5; if (info->disassembler_options + && strstr (info->disassembler_options, "cell") != NULL) + dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC; + + if (info->disassembler_options && strstr (info->disassembler_options, "power6") != NULL) dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC; diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 84e6d6a04e9..acfeb8ccfd9 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -1823,6 +1823,7 @@ extract_tbr (unsigned long insn, #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM #define POWER4 PPC_OPCODE_POWER4 #define POWER5 PPC_OPCODE_POWER5 +#define CELL PPC_OPCODE_CELL #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC #define PPC403 PPC_OPCODE_403 @@ -3014,7 +3015,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, -{ "hrfid", XL(19,274), 0xffffffff, POWER5, { 0 } }, +{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } }, { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, @@ -3622,7 +3623,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, -{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } }, +{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } }, { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } }, @@ -4206,6 +4207,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, +{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } }, + { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } }, { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, @@ -4265,6 +4268,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, +{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } }, + { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } }, { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } }, @@ -4423,6 +4428,16 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, +/* New load/store left/right index vector instructions that are in the Cell only. */ +{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } }, +{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } }, +{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } }, +{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } }, +{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } }, +{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } }, +{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } }, +{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } }, + { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } }, { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } }, |