diff options
author | Mark Loeser <halcy0n@gentoo.org> | 2008-05-07 01:49:12 +0000 |
---|---|---|
committer | Mark Loeser <halcy0n@gentoo.org> | 2008-05-07 01:49:12 +0000 |
commit | aa95227014aa807f80691ec74d58579ccbb35354 (patch) | |
tree | 36347b525847bbe5d7b8efbb00d8255aaf5a8e66 /sci-electronics | |
parent | Fix grammar for seemant. (diff) | |
download | gentoo-2-aa95227014aa807f80691ec74d58579ccbb35354.tar.gz gentoo-2-aa95227014aa807f80691ec74d58579ccbb35354.tar.bz2 gentoo-2-aa95227014aa807f80691ec74d58579ccbb35354.zip |
Fix compilation with gcc-4.3 by Devils-Hawk <dev AT stuffit DOT at>; bug #206076
(Portage version: 2.1.5_rc7)
Diffstat (limited to 'sci-electronics')
-rw-r--r-- | sci-electronics/iverilog/ChangeLog | 9 | ||||
-rw-r--r-- | sci-electronics/iverilog/files/iverilog-gcc43.patch | 177 | ||||
-rw-r--r-- | sci-electronics/iverilog/iverilog-0.8.6.ebuild | 8 |
3 files changed, 189 insertions, 5 deletions
diff --git a/sci-electronics/iverilog/ChangeLog b/sci-electronics/iverilog/ChangeLog index 196953c0ca30..4269365869fd 100644 --- a/sci-electronics/iverilog/ChangeLog +++ b/sci-electronics/iverilog/ChangeLog @@ -1,6 +1,11 @@ # ChangeLog for sci-electronics/iverilog -# Copyright 2002-2007 Gentoo Foundation; Distributed under the GPL v2 -# $Header: /var/cvsroot/gentoo-x86/sci-electronics/iverilog/ChangeLog,v 1.20 2007/11/30 09:11:22 calchan Exp $ +# Copyright 2002-2008 Gentoo Foundation; Distributed under the GPL v2 +# $Header: /var/cvsroot/gentoo-x86/sci-electronics/iverilog/ChangeLog,v 1.21 2008/05/07 01:49:12 halcy0n Exp $ + + 07 May 2008; Mark Loeser <halcy0n@gentoo.org> +files/iverilog-gcc43.patch, + iverilog-0.8.6.ebuild: + Fix compilation with gcc-4.3 by Devils-Hawk <dev AT stuffit DOT at>; bug + #206076 *iverilog-0.8.6 (30 Nov 2007) diff --git a/sci-electronics/iverilog/files/iverilog-gcc43.patch b/sci-electronics/iverilog/files/iverilog-gcc43.patch new file mode 100644 index 000000000000..960ba01c8dc2 --- /dev/null +++ b/sci-electronics/iverilog/files/iverilog-gcc43.patch @@ -0,0 +1,177 @@ +diff -rup verilog-0.8.6/elab_net.cc verilog-0.8.6-devel/elab_net.cc +--- verilog-0.8.6/elab_net.cc 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/elab_net.cc 2008-01-16 12:02:42.000000000 +0100 +@@ -28,6 +28,7 @@ + # include "compiler.h" + + # include <iostream> ++# include <cstring> + + /* + * This is a state flag that determines whether an elaborate_net must +diff -rup verilog-0.8.6/elab_scope.cc verilog-0.8.6-devel/elab_scope.cc +--- verilog-0.8.6/elab_scope.cc 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/elab_scope.cc 2008-01-16 12:03:34.000000000 +0100 +@@ -24,6 +24,7 @@ + # include "compiler.h" + # include <iostream> + # include <stdio.h> ++# include <cstring> + + /* + * Elaboration happens in two passes, generally. The first scans the +diff -rup verilog-0.8.6/elab_sig.cc verilog-0.8.6-devel/elab_sig.cc +--- verilog-0.8.6/elab_sig.cc 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/elab_sig.cc 2008-01-16 12:04:05.000000000 +0100 +@@ -23,6 +23,7 @@ + # include "config.h" + + # include <iostream> ++# include <cstdlib> + + # include "Module.h" + # include "PExpr.h" +diff -rup verilog-0.8.6/emit.cc verilog-0.8.6-devel/emit.cc +--- verilog-0.8.6/emit.cc 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/emit.cc 2008-01-16 12:04:40.000000000 +0100 +@@ -32,6 +32,7 @@ + # include "netlist.h" + # include <typeinfo> + # include <cassert> ++# include <cstring> + + bool NetNode::emit_node(struct target_t*tgt) const + { +diff -rup verilog-0.8.6/load_module.cc verilog-0.8.6-devel/load_module.cc +--- verilog-0.8.6/load_module.cc 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/load_module.cc 2008-01-16 12:05:21.000000000 +0100 +@@ -31,6 +31,8 @@ + # include <dirent.h> + # include <ctype.h> + # include <assert.h> ++# include <cstdlib> ++# include <cstring> + + /* + * The module library items are maps of key names to file name within +diff -rup verilog-0.8.6/net_design.cc verilog-0.8.6-devel/net_design.cc +--- verilog-0.8.6/net_design.cc 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/net_design.cc 2008-01-16 12:05:46.000000000 +0100 +@@ -33,6 +33,7 @@ + # include "util.h" + # include "compiler.h" + # include <sstream> ++# include <cstring> + + Design:: Design() + : errors(0), nodes_(0), procs_(0), lcounter_(0) +diff -rup verilog-0.8.6/net_link.cc verilog-0.8.6-devel/net_link.cc +--- verilog-0.8.6/net_link.cc 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/net_link.cc 2008-01-16 12:06:28.000000000 +0100 +@@ -27,6 +27,7 @@ + # include "netlist.h" + # include <sstream> + # include <string> ++# include <cstring> + # include <typeinfo> + #ifdef HAVE_MALLOC_H + # include <malloc.h> +diff -rup verilog-0.8.6/net_scope.cc verilog-0.8.6-devel/net_scope.cc +--- verilog-0.8.6/net_scope.cc 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/net_scope.cc 2008-01-16 12:06:56.000000000 +0100 +@@ -25,6 +25,7 @@ + + # include "netlist.h" + # include <sstream> ++# include <cstring> + + /* + * The NetScope class keeps a scope tree organized. Each node of the +diff -rup verilog-0.8.6/pform.h verilog-0.8.6-devel/pform.h +--- verilog-0.8.6/pform.h 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/pform.h 2008-01-16 11:58:59.000000000 +0100 +@@ -37,6 +37,8 @@ + # include <string> + # include <list> + # include <stdio.h> ++# include <cstring> ++# include <cstdlib> + + /* + * These classes implement the parsed form (P-form for short) of the +diff -rup verilog-0.8.6/synth2.cc verilog-0.8.6-devel/synth2.cc +--- verilog-0.8.6/synth2.cc 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/synth2.cc 2008-01-16 12:11:00.000000000 +0100 +@@ -28,6 +28,7 @@ + #include <cassert> + #include "NetLatch.h" + #include <climits> ++#include <cstdlib> + + #include <new> // standard operator new + using std::bad_alloc; +diff -rup verilog-0.8.6/sys_funcs.cc verilog-0.8.6-devel/sys_funcs.cc +--- verilog-0.8.6/sys_funcs.cc 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/sys_funcs.cc 2008-01-16 12:07:31.000000000 +0100 +@@ -23,6 +23,8 @@ + # include "config.h" + # include "compiler.h" + # include <stdio.h> ++# include <cstdlib> ++# include <cstring> + + /* + * Manage the information about system functions. This information is +diff -rup verilog-0.8.6/t-dll.cc verilog-0.8.6-devel/t-dll.cc +--- verilog-0.8.6/t-dll.cc 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/t-dll.cc 2008-01-16 12:11:25.000000000 +0100 +@@ -31,7 +31,8 @@ + #ifdef HAVE_MALLOC_H + # include <malloc.h> + #endif +-# include <stdlib.h> ++# include <cstdlib> ++# include <cstring> + + #include <new> // standard operator new + using std::bad_alloc; +diff -rup verilog-0.8.6/t-dll-expr.cc verilog-0.8.6-devel/t-dll-expr.cc +--- verilog-0.8.6/t-dll-expr.cc 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/t-dll-expr.cc 2008-01-16 12:11:54.000000000 +0100 +@@ -30,7 +30,8 @@ + #ifdef HAVE_MALLOC_H + # include <malloc.h> + #endif +-# include <stdlib.h> ++# include <cstdlib> ++# include <cstring> + + /* + * This is a little convenience function for converting a NetExpr +diff -rup verilog-0.8.6/t-dll-proc.cc verilog-0.8.6-devel/t-dll-proc.cc +--- verilog-0.8.6/t-dll-proc.cc 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/t-dll-proc.cc 2008-01-16 12:12:29.000000000 +0100 +@@ -32,7 +32,8 @@ + #ifdef HAVE_MALLOC_H + # include <malloc.h> + #endif +-# include <stdlib.h> ++# include <cstdlib> ++# include <cstring> + + + bool dll_target::process(const NetProcTop*net) +diff -rup verilog-0.8.6/verireal.cc verilog-0.8.6-devel/verireal.cc +--- verilog-0.8.6/verireal.cc 2007-11-26 19:55:13.000000000 +0100 ++++ verilog-0.8.6-devel/verireal.cc 2008-01-16 12:07:58.000000000 +0100 +@@ -24,7 +24,8 @@ + + # include "verireal.h" + # include "verinum.h" +-# include <stdlib.h> ++# include <cstdlib> ++# include <cstring> + # include <ctype.h> + # include <iostream> + # include <math.h> + diff --git a/sci-electronics/iverilog/iverilog-0.8.6.ebuild b/sci-electronics/iverilog/iverilog-0.8.6.ebuild index 7736bc3429c5..0fb491fe36ae 100644 --- a/sci-electronics/iverilog/iverilog-0.8.6.ebuild +++ b/sci-electronics/iverilog/iverilog-0.8.6.ebuild @@ -1,8 +1,8 @@ -# Copyright 1999-2007 Gentoo Foundation +# Copyright 1999-2008 Gentoo Foundation # Distributed under the terms of the GNU General Public License v2 -# $Header: /var/cvsroot/gentoo-x86/sci-electronics/iverilog/iverilog-0.8.6.ebuild,v 1.1 2007/11/30 09:11:22 calchan Exp $ +# $Header: /var/cvsroot/gentoo-x86/sci-electronics/iverilog/iverilog-0.8.6.ebuild,v 1.2 2008/05/07 01:49:12 halcy0n Exp $ -inherit multilib +inherit eutils multilib S="${WORKDIR}/verilog-${PV}" @@ -22,6 +22,8 @@ src_unpack() { unpack ${A} cd "${S}" + epatch "${FILESDIR}"/iverilog-gcc43.patch + # Fix for bug #172919 sed -i -e '/# include <asm\/page.h>/d' vvp/main.cc || die "sed failed" } |