From 9ebe2ba83644ec6cd33a93c68dab5f551adcbea0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Date: Tue, 7 Jun 2022 14:04:16 +0200 Subject: [PATCH 14/51] x86/msr: handle reads to MSR_P5_MC_{ADDR,TYPE} MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Windows Server 2019 Essentials will unconditionally attempt to read P5_MC_ADDR MSR at boot and throw a BSOD if injected a #GP. Fix this by mapping MSR_P5_MC_{ADDR,TYPE} to MSR_IA32_MCi_{ADDR,STATUS}, as reported also done by hardware in Intel SDM "Mapping of the Pentium Processor Machine-Check Errors to the Machine-Check Architecture" section. Reported-by: Steffen Einsle Signed-off-by: Roger Pau Monné Reviewed-by: Jan Beulich master commit: ce59e472b581e4923f6892172dde62b88c8aa8b7 master date: 2022-05-02 08:49:12 +0200 --- xen/arch/x86/cpu/mcheck/mce.h | 6 ++++++ xen/arch/x86/cpu/mcheck/mce_intel.c | 19 +++++++++++++++++++ xen/arch/x86/cpu/mcheck/vmce.c | 2 ++ xen/arch/x86/msr.c | 2 ++ xen/include/asm-x86/msr-index.h | 3 +++ 5 files changed, 32 insertions(+) diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 195362691904..192315ecfa3d 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -169,6 +169,12 @@ static inline int mce_vendor_bank_msr(const struct vcpu *v, uint32_t msr) if (msr >= MSR_IA32_MC0_CTL2 && msr < MSR_IA32_MCx_CTL2(v->arch.vmce.mcg_cap & MCG_CAP_COUNT) ) return 1; + fallthrough; + + case X86_VENDOR_CENTAUR: + case X86_VENDOR_SHANGHAI: + if (msr == MSR_P5_MC_ADDR || msr == MSR_P5_MC_TYPE) + return 1; break; case X86_VENDOR_AMD: diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index bb9f3a3ff795..d364e9bf5ad1 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -1001,8 +1001,27 @@ int vmce_intel_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) int vmce_intel_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) { + const struct cpuid_policy *cp = v->domain->arch.cpuid; unsigned int bank = msr - MSR_IA32_MC0_CTL2; + switch ( msr ) + { + case MSR_P5_MC_ADDR: + /* + * Bank 0 is used for the 'bank 0 quirk' on older processors. + * See vcpu_fill_mc_msrs() for reference. + */ + *val = v->arch.vmce.bank[1].mci_addr; + return 1; + + case MSR_P5_MC_TYPE: + *val = v->arch.vmce.bank[1].mci_status; + return 1; + } + + if ( !(cp->x86_vendor & X86_VENDOR_INTEL) ) + return 0; + if ( bank < GUEST_MC_BANK_NUM ) { *val = v->arch.vmce.bank[bank].mci_ctl2; diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index eb6434a3ba20..0899df58bcbf 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -150,6 +150,8 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) default: switch ( boot_cpu_data.x86_vendor ) { + case X86_VENDOR_CENTAUR: + case X86_VENDOR_SHANGHAI: case X86_VENDOR_INTEL: ret = vmce_intel_rdmsr(v, msr, val); break; diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index aaedb2c31287..da305c7aa4c9 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -282,6 +282,8 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) *val = msrs->misc_features_enables.raw; break; + case MSR_P5_MC_ADDR: + case MSR_P5_MC_TYPE: case MSR_IA32_MCG_CAP ... MSR_IA32_MCG_CTL: /* 0x179 -> 0x17b */ case MSR_IA32_MCx_CTL2(0) ... MSR_IA32_MCx_CTL2(31): /* 0x280 -> 0x29f */ case MSR_IA32_MCx_CTL(0) ... MSR_IA32_MCx_MISC(31): /* 0x400 -> 0x47f */ diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 3e038db618ff..31964b88af7a 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -15,6 +15,9 @@ * abbreviated name. Exceptions will be considered on a case-by-case basis. */ +#define MSR_P5_MC_ADDR 0 +#define MSR_P5_MC_TYPE 0x00000001 + #define MSR_APIC_BASE 0x0000001b #define APIC_BASE_BSP (_AC(1, ULL) << 8) #define APIC_BASE_EXTD (_AC(1, ULL) << 10) -- 2.35.1