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authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2008-02-12 21:01:26 +0000
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2008-02-12 21:01:26 +0000
commitd0dc7dc3274a88db1c9941614454ed842d62cf91 (patch)
tree46e369f2d52daecef62ef93665fdc6dbb21c3b82 /linux-user/mips
parent Fix SS-20 auxio addresses (diff)
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Make MIPS MT implementation more cache friendly.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3981 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'linux-user/mips')
-rw-r--r--linux-user/mips/target_signal.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/linux-user/mips/target_signal.h b/linux-user/mips/target_signal.h
index 3b06e9824..f3ef38d24 100644
--- a/linux-user/mips/target_signal.h
+++ b/linux-user/mips/target_signal.h
@@ -23,7 +23,7 @@ typedef struct target_sigaltstack {
static inline abi_ulong get_sp_from_cpustate(CPUMIPSState *state)
{
- return state->gpr[29][state->current_tc];
+ return state->gpr[state->current_tc][29];
}
#endif /* TARGET_SIGNAL_H */