diff options
author | 2021-04-20 15:47:54 +0800 | |
---|---|---|
committer | 2021-04-20 15:49:52 +0800 | |
commit | b8203397522fee82e5c79700b80837aed468dfad (patch) | |
tree | b0cd69dc21e4c695fc9be3c4a17d2b358b94e375 | |
parent | [SelectionDAG] Relax constraints on STEP_VECTOR step operand (diff) | |
download | llvm-project-b8203397522fee82e5c79700b80837aed468dfad.tar.gz llvm-project-b8203397522fee82e5c79700b80837aed468dfad.tar.bz2 llvm-project-b8203397522fee82e5c79700b80837aed468dfad.zip |
[PowerPC] Support f128 under VSX
This patch is the last one in backend to support fp128 type in
pre-POWER9 subtargets with VSX, removing temporary option and updating
remaining tests.
Reviewed By: steven.zhang
Differential Revision: https://reviews.llvm.org/D92374
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 54 | ||||
-rw-r--r-- | llvm/test/CodeGen/PowerPC/f128-aggregates.ll | 160 | ||||
-rw-r--r-- | llvm/test/CodeGen/PowerPC/f128-arith.ll | 2 | ||||
-rw-r--r-- | llvm/test/CodeGen/PowerPC/f128-bitcast.ll | 11 | ||||
-rw-r--r-- | llvm/test/CodeGen/PowerPC/f128-compare.ll | 2 | ||||
-rw-r--r-- | llvm/test/CodeGen/PowerPC/f128-conv.ll | 2 | ||||
-rw-r--r-- | llvm/test/CodeGen/PowerPC/f128-fma.ll | 332 | ||||
-rw-r--r-- | llvm/test/CodeGen/PowerPC/f128-passByValue.ll | 480 | ||||
-rw-r--r-- | llvm/test/CodeGen/PowerPC/f128-rounding.ll | 2 | ||||
-rw-r--r-- | llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll | 233 | ||||
-rw-r--r-- | llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll | 10 | ||||
-rw-r--r-- | llvm/test/CodeGen/PowerPC/fp-strict-f128.ll | 57 | ||||
-rw-r--r-- | llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll | 2 | ||||
-rw-r--r-- | llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll | 1766 | ||||
-rw-r--r-- | llvm/test/CodeGen/PowerPC/store_fptoi.ll | 20 |
15 files changed, 1499 insertions, 1634 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index d4efb2ba6651..c62fedf93fc9 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -121,11 +121,6 @@ cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden); static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables", cl::desc("use absolute jump tables on ppc"), cl::Hidden); -// TODO - Remove this option if soft fp128 has been fully supported . -static cl::opt<bool> - EnableSoftFP128("enable-soft-fp128", - cl::desc("temp option to enable soft fp128"), cl::Hidden); - STATISTIC(NumTailCalls, "Number of tail calls"); STATISTIC(NumSiblingCalls, "Number of sibling calls"); STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM"); @@ -1102,6 +1097,23 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal); addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass); + addRegisterClass(MVT::f128, &PPC::VRRCRegClass); + + for (MVT FPT : MVT::fp_valuetypes()) + setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand); + + // Expand the SELECT to SELECT_CC + setOperationAction(ISD::SELECT, MVT::f128, Expand); + + setTruncStoreAction(MVT::f128, MVT::f64, Expand); + setTruncStoreAction(MVT::f128, MVT::f32, Expand); + + // No implementation for these ops for PowerPC. + setOperationAction(ISD::FSIN, MVT::f128, Expand); + setOperationAction(ISD::FCOS, MVT::f128, Expand); + setOperationAction(ISD::FPOW, MVT::f128, Expand); + setOperationAction(ISD::FPOWI, MVT::f128, Expand); + setOperationAction(ISD::FREM, MVT::f128, Expand); } if (Subtarget.hasP8Altivec()) { @@ -1120,15 +1132,12 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::SRL, MVT::v1i128, Legal); setOperationAction(ISD::SRA, MVT::v1i128, Expand); - addRegisterClass(MVT::f128, &PPC::VRRCRegClass); setOperationAction(ISD::FADD, MVT::f128, Legal); setOperationAction(ISD::FSUB, MVT::f128, Legal); setOperationAction(ISD::FDIV, MVT::f128, Legal); setOperationAction(ISD::FMUL, MVT::f128, Legal); setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); - // No extending loads to f128 on PPC. - for (MVT FPT : MVT::fp_valuetypes()) - setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand); + setOperationAction(ISD::FMA, MVT::f128, Legal); setCondCodeAction(ISD::SETULT, MVT::f128, Expand); setCondCodeAction(ISD::SETUGT, MVT::f128, Expand); @@ -1144,18 +1153,9 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal); setOperationAction(ISD::FROUND, MVT::f128, Legal); - setOperationAction(ISD::SELECT, MVT::f128, Expand); setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); - setTruncStoreAction(MVT::f128, MVT::f64, Expand); - setTruncStoreAction(MVT::f128, MVT::f32, Expand); setOperationAction(ISD::BITCAST, MVT::i128, Custom); - // No implementation for these ops for PowerPC. - setOperationAction(ISD::FSIN, MVT::f128, Expand); - setOperationAction(ISD::FCOS, MVT::f128, Expand); - setOperationAction(ISD::FPOW, MVT::f128, Expand); - setOperationAction(ISD::FPOWI, MVT::f128, Expand); - setOperationAction(ISD::FREM, MVT::f128, Expand); // Handle constrained floating-point operations of fp128 setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal); @@ -1178,12 +1178,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::BSWAP, MVT::v4i32, Legal); setOperationAction(ISD::BSWAP, MVT::v2i64, Legal); setOperationAction(ISD::BSWAP, MVT::v1i128, Legal); - } else if (Subtarget.hasAltivec() && EnableSoftFP128) { - addRegisterClass(MVT::f128, &PPC::VRRCRegClass); - - for (MVT FPT : MVT::fp_valuetypes()) - setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand); - + } else if (Subtarget.hasVSX()) { setOperationAction(ISD::LOAD, MVT::f128, Promote); setOperationAction(ISD::STORE, MVT::f128, Promote); @@ -1199,18 +1194,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::FDIV, MVT::f128, Expand); setOperationAction(ISD::FNEG, MVT::f128, Expand); setOperationAction(ISD::FABS, MVT::f128, Expand); - setOperationAction(ISD::FSIN, MVT::f128, Expand); - setOperationAction(ISD::FCOS, MVT::f128, Expand); - setOperationAction(ISD::FPOW, MVT::f128, Expand); - setOperationAction(ISD::FPOWI, MVT::f128, Expand); - setOperationAction(ISD::FREM, MVT::f128, Expand); setOperationAction(ISD::FSQRT, MVT::f128, Expand); setOperationAction(ISD::FMA, MVT::f128, Expand); setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); - setTruncStoreAction(MVT::f128, MVT::f64, Expand); - setTruncStoreAction(MVT::f128, MVT::f32, Expand); - // Expand the fp_extend if the target type is fp128. setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand); setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Expand); @@ -14132,6 +14119,9 @@ SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N, (Op1VT == MVT::i32 || Op1VT == MVT::i64 || (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); + if (ResVT == MVT::f128 && !Subtarget.hasP9Vector()) + return SDValue(); + if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() || cast<StoreSDNode>(N)->isTruncatingStore() || !ValidTypeForStoreFltAsInt) return SDValue(); diff --git a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll index 0a23f7ad460d..0172042a044c 100644 --- a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll +++ b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll @@ -30,9 +30,8 @@ define fp128 @testArray_01(fp128* nocapture readonly %sa) { ; ; CHECK-P8-LABEL: testArray_01: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: ld r5, 32(r3) -; CHECK-P8-NEXT: ld r4, 40(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: addi r3, r3, 32 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: blr entry: @@ -60,9 +59,9 @@ define fp128 @testArray_02() { ; CHECK-P8-LABEL: testArray_02: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r3, r2, .LC0@toc@ha -; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r3) -; CHECK-P8-NEXT: ld r3, 32(r4) -; CHECK-P8-NEXT: ld r4, 40(r4) +; CHECK-P8-NEXT: ld r3, .LC0@toc@l(r3) +; CHECK-P8-NEXT: addi r3, r3, 32 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: blr entry: @@ -103,8 +102,7 @@ define fp128 @testStruct_02([8 x fp128] %a.coerce) { ; ; CHECK-P8-LABEL: testStruct_02: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: ld r3, 144(r1) -; CHECK-P8-NEXT: ld r4, 152(r1) +; CHECK-P8-NEXT: vmr v2, v9 ; CHECK-P8-NEXT: blr entry: @@ -144,14 +142,13 @@ define fp128 @testStruct_03(%struct.With9fp128params* byval(%struct.With9fp128pa ; ; CHECK-P8-LABEL: testStruct_03: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: ld r11, 128(r1) -; CHECK-P8-NEXT: ld r12, 136(r1) +; CHECK-P8-NEXT: li r11, 96 +; CHECK-P8-NEXT: addi r12, r1, 32 ; CHECK-P8-NEXT: std r3, 32(r1) ; CHECK-P8-NEXT: std r4, 40(r1) ; CHECK-P8-NEXT: std r5, 48(r1) ; CHECK-P8-NEXT: std r6, 56(r1) -; CHECK-P8-NEXT: mr r3, r11 -; CHECK-P8-NEXT: mr r4, r12 +; CHECK-P8-NEXT: lvx v2, r12, r11 ; CHECK-P8-NEXT: std r7, 64(r1) ; CHECK-P8-NEXT: std r8, 72(r1) ; CHECK-P8-NEXT: std r9, 80(r1) @@ -179,8 +176,7 @@ define fp128 @testStruct_04([8 x fp128] %a.coerce) { ; ; CHECK-P8-LABEL: testStruct_04: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: mr r4, r10 -; CHECK-P8-NEXT: mr r3, r9 +; CHECK-P8-NEXT: vmr v2, v5 ; CHECK-P8-NEXT: blr entry: @@ -240,8 +236,7 @@ define fp128 @testHUnion_03([3 x fp128] %a.coerce) { ; ; CHECK-P8-LABEL: testHUnion_03: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: mr r4, r6 -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: vmr v2, v3 ; CHECK-P8-NEXT: blr entry: @@ -263,8 +258,7 @@ define fp128 @testHUnion_04([3 x fp128] %a.coerce) { ; ; CHECK-P8-LABEL: testHUnion_04: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: mr r4, r8 -; CHECK-P8-NEXT: mr r3, r7 +; CHECK-P8-NEXT: vmr v2, v4 ; CHECK-P8-NEXT: blr entry: @@ -291,8 +285,10 @@ define fp128 @testMixedAggregate([3 x i128] %a.coerce) { ; ; CHECK-P8-LABEL: testMixedAggregate: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: mr r4, r8 -; CHECK-P8-NEXT: mr r3, r7 +; CHECK-P8-NEXT: addi r3, r1, -16 +; CHECK-P8-NEXT: std r8, -8(r1) +; CHECK-P8-NEXT: std r7, -16(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: blr entry: @@ -315,8 +311,10 @@ define fp128 @testMixedAggregate_02([4 x i128] %a.coerce) { ; ; CHECK-P8-LABEL: testMixedAggregate_02: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: mr r4, r6 -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: addi r3, r1, -16 +; CHECK-P8-NEXT: std r6, -8(r1) +; CHECK-P8-NEXT: std r5, -16(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: blr entry: @@ -352,44 +350,40 @@ define fp128 @testMixedAggregate_03([4 x i128] %sa.coerce) { ; CHECK-P8-LABEL: testMixedAggregate_03: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -96(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 96 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r28, -32 -; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r30, -16 -; CHECK-P8-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -64(r1) +; CHECK-P8-NEXT: .cfi_offset v31, -32 +; CHECK-P8-NEXT: li r4, 64 +; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: mr r30, r10 -; CHECK-P8-NEXT: mr r29, r6 -; CHECK-P8-NEXT: mr r28, r5 +; CHECK-P8-NEXT: stvx v31, r1, r4 # 16-byte Folded Spill +; CHECK-P8-NEXT: addi r4, r1, 48 +; CHECK-P8-NEXT: std r6, 56(r1) +; CHECK-P8-NEXT: std r5, 48(r1) +; CHECK-P8-NEXT: lvx v31, 0, r4 ; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r3 -; CHECK-P8-NEXT: mr r6, r4 -; CHECK-P8-NEXT: mr r3, r28 -; CHECK-P8-NEXT: mr r4, r29 +; CHECK-P8-NEXT: vmr v3, v2 +; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r3, r30 -; CHECK-P8-NEXT: mr r28, r4 +; CHECK-P8-NEXT: vmr v31, v2 ; CHECK-P8-NEXT: bl __floatdikf ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r3 -; CHECK-P8-NEXT: mr r6, r4 -; CHECK-P8-NEXT: mr r3, r29 -; CHECK-P8-NEXT: mr r4, r28 +; CHECK-P8-NEXT: vmr v3, v2 +; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: li r3, 64 +; CHECK-P8-NEXT: ld r30, 80(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: addi r1, r1, 96 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr entry: @@ -438,16 +432,17 @@ define fp128 @testNestedAggregate(%struct.MixedC* byval(%struct.MixedC) nocaptur ; ; CHECK-P8-LABEL: testNestedAggregate: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: std r3, 32(r1) -; CHECK-P8-NEXT: std r4, 40(r1) -; CHECK-P8-NEXT: mr r3, r7 -; CHECK-P8-NEXT: mr r4, r8 +; CHECK-P8-NEXT: li r11, 32 ; CHECK-P8-NEXT: std r8, 72(r1) ; CHECK-P8-NEXT: std r7, 64(r1) -; CHECK-P8-NEXT: std r5, 48(r1) -; CHECK-P8-NEXT: std r6, 56(r1) ; CHECK-P8-NEXT: std r9, 80(r1) ; CHECK-P8-NEXT: std r10, 88(r1) +; CHECK-P8-NEXT: addi r7, r1, 32 +; CHECK-P8-NEXT: lvx v2, r7, r11 +; CHECK-P8-NEXT: std r3, 32(r1) +; CHECK-P8-NEXT: std r4, 40(r1) +; CHECK-P8-NEXT: std r5, 48(r1) +; CHECK-P8-NEXT: std r6, 56(r1) ; CHECK-P8-NEXT: blr entry: @@ -470,6 +465,10 @@ define fp128 @testUnion_01([1 x i128] %a.coerce) { ; ; CHECK-P8-LABEL: testUnion_01: ; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addi r5, r1, -16 +; CHECK-P8-NEXT: std r4, -8(r1) +; CHECK-P8-NEXT: std r3, -16(r1) +; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: blr entry: @@ -492,6 +491,10 @@ define fp128 @testUnion_02([1 x i128] %a.coerce) { ; ; CHECK-P8-LABEL: testUnion_02: ; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: addi r5, r1, -16 +; CHECK-P8-NEXT: std r4, -8(r1) +; CHECK-P8-NEXT: std r3, -16(r1) +; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: blr entry: @@ -514,8 +517,10 @@ define fp128 @testUnion_03([4 x i128] %a.coerce) { ; ; CHECK-P8-LABEL: testUnion_03: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: mr r4, r8 -; CHECK-P8-NEXT: mr r3, r7 +; CHECK-P8-NEXT: addi r3, r1, -16 +; CHECK-P8-NEXT: std r8, -8(r1) +; CHECK-P8-NEXT: std r7, -16(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: blr entry: @@ -577,39 +582,44 @@ define fp128 @sum_float128(i32 signext %count, ...) { ; CHECK-P8-LABEL: sum_float128: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 +; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_offset lr, 16 +; CHECK-P8-NEXT: .cfi_offset r30, -16 +; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -64(r1) +; CHECK-P8-NEXT: addis r11, r2, .LCPI17_0@toc@ha ; CHECK-P8-NEXT: cmpwi r3, 1 -; CHECK-P8-NEXT: std r4, 88(r1) -; CHECK-P8-NEXT: std r5, 96(r1) -; CHECK-P8-NEXT: std r6, 104(r1) -; CHECK-P8-NEXT: std r7, 112(r1) -; CHECK-P8-NEXT: std r8, 120(r1) -; CHECK-P8-NEXT: std r9, 128(r1) -; CHECK-P8-NEXT: std r10, 136(r1) +; CHECK-P8-NEXT: std r4, 104(r1) +; CHECK-P8-NEXT: std r5, 112(r1) +; CHECK-P8-NEXT: std r6, 120(r1) +; CHECK-P8-NEXT: std r7, 128(r1) +; CHECK-P8-NEXT: addi r3, r11, .LCPI17_0@toc@l +; CHECK-P8-NEXT: std r8, 136(r1) +; CHECK-P8-NEXT: std r9, 144(r1) +; CHECK-P8-NEXT: std r10, 152(r1) ; CHECK-P8-NEXT: blt cr0, .LBB17_2 ; CHECK-P8-NEXT: # %bb.1: # %if.end -; CHECK-P8-NEXT: ld r3, 88(r1) -; CHECK-P8-NEXT: ld r4, 96(r1) -; CHECK-P8-NEXT: li r5, 0 -; CHECK-P8-NEXT: li r6, 0 +; CHECK-P8-NEXT: addi r30, r1, 104 +; CHECK-P8-NEXT: lvx v3, 0, r3 +; CHECK-P8-NEXT: lxvd2x vs0, 0, r30 +; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: ld r5, 104(r1) -; CHECK-P8-NEXT: ld r6, 112(r1) -; CHECK-P8-NEXT: addi r7, r1, 120 -; CHECK-P8-NEXT: std r7, 40(r1) +; CHECK-P8-NEXT: li r3, 16 +; CHECK-P8-NEXT: lxvd2x vs0, r30, r3 +; CHECK-P8-NEXT: addi r3, r1, 136 +; CHECK-P8-NEXT: std r3, 40(r1) +; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: b .LBB17_3 ; CHECK-P8-NEXT: .LBB17_2: -; CHECK-P8-NEXT: li r3, 0 -; CHECK-P8-NEXT: li r4, 0 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: .LBB17_3: # %cleanup -; CHECK-P8-NEXT: addi r1, r1, 48 +; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: ld r0, 16(r1) +; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr entry: diff --git a/llvm/test/CodeGen/PowerPC/f128-arith.ll b/llvm/test/CodeGen/PowerPC/f128-arith.ll index fa8463f5e184..be6c1ea585d9 100644 --- a/llvm/test/CodeGen/PowerPC/f128-arith.ll +++ b/llvm/test/CodeGen/PowerPC/f128-arith.ll @@ -2,7 +2,7 @@ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \ ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \ -; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -enable-soft-fp128 | FileCheck %s \ +; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s \ ; RUN: -check-prefix=CHECK-P8 ; Function Attrs: norecurse nounwind diff --git a/llvm/test/CodeGen/PowerPC/f128-bitcast.ll b/llvm/test/CodeGen/PowerPC/f128-bitcast.ll index 01cbd1a42419..f412fc36ecc9 100644 --- a/llvm/test/CodeGen/PowerPC/f128-bitcast.ll +++ b/llvm/test/CodeGen/PowerPC/f128-bitcast.ll @@ -22,6 +22,8 @@ define i64 @getPart1(fp128 %in) local_unnamed_addr { ; ; CHECK-P8-LABEL: getPart1: ; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: xxswapd vs0, v2 +; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: blr entry: %0 = bitcast fp128 %in to i128 @@ -43,7 +45,7 @@ define i64 @getPart2(fp128 %in) local_unnamed_addr { ; ; CHECK-P8-LABEL: getPart2: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: mr r3, r4 +; CHECK-P8-NEXT: mfvsrd r3, v2 ; CHECK-P8-NEXT: blr entry: %0 = bitcast fp128 %in to i128 @@ -70,11 +72,8 @@ define i64 @checkBitcast(fp128 %in, <2 x i64> %in2, <2 x i64> *%out) local_unnam ; ; CHECK-P8-LABEL: checkBitcast: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: mtfprd f0, r3 -; CHECK-P8-NEXT: mtfprd f1, r4 -; CHECK-P8-NEXT: xxmrghd v3, vs1, vs0 -; CHECK-P8-NEXT: xxswapd vs0, v3 -; CHECK-P8-NEXT: vaddudm v2, v3, v2 +; CHECK-P8-NEXT: xxswapd vs0, v2 +; CHECK-P8-NEXT: vaddudm v2, v2, v3 ; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r7 diff --git a/llvm/test/CodeGen/PowerPC/f128-compare.ll b/llvm/test/CodeGen/PowerPC/f128-compare.ll index 869b5182b3a8..f27a4dacfdec 100644 --- a/llvm/test/CodeGen/PowerPC/f128-compare.ll +++ b/llvm/test/CodeGen/PowerPC/f128-compare.ll @@ -2,7 +2,7 @@ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \ ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \ -; RUN: -enable-soft-fp128 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s \ +; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s \ ; RUN: -check-prefix=CHECK-P8 @a_qp = common dso_local global fp128 0xL00000000000000000000000000000000, align 16 diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll b/llvm/test/CodeGen/PowerPC/f128-conv.ll index a6bc5d47987b..2e34bb606dda 100644 --- a/llvm/test/CodeGen/PowerPC/f128-conv.ll +++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll @@ -4,7 +4,7 @@ ; RUN: | FileCheck %s ; RUN: llc -relocation-model=pic -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ ; RUN: -ppc-vsr-nums-as-vr -verify-machineinstrs -ppc-asm-full-reg-names < %s \ -; RUN: -enable-soft-fp128 | FileCheck %s -check-prefix=CHECK-P8 +; RUN: | FileCheck %s -check-prefix=CHECK-P8 @mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8 @umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8 diff --git a/llvm/test/CodeGen/PowerPC/f128-fma.ll b/llvm/test/CodeGen/PowerPC/f128-fma.ll index 7f49bcc38157..048711820c0f 100644 --- a/llvm/test/CodeGen/PowerPC/f128-fma.ll +++ b/llvm/test/CodeGen/PowerPC/f128-fma.ll @@ -18,40 +18,30 @@ define void @qpFmadd(fp128* nocapture readonly %a, fp128* nocapture %b, ; CHECK-P8-LABEL: qpFmadd: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -80(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r28, -32 -; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r30, -16 -; CHECK-P8-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: ld r7, 0(r3) -; CHECK-P8-NEXT: ld r8, 8(r3) -; CHECK-P8-NEXT: ld r9, 0(r4) -; CHECK-P8-NEXT: ld r10, 8(r4) -; CHECK-P8-NEXT: mr r28, r6 -; CHECK-P8-NEXT: ld r30, 0(r5) -; CHECK-P8-NEXT: ld r29, 8(r5) -; CHECK-P8-NEXT: mr r3, r7 -; CHECK-P8-NEXT: mr r4, r8 -; CHECK-P8-NEXT: mr r5, r9 -; CHECK-P8-NEXT: mr r6, r10 +; CHECK-P8-NEXT: .cfi_offset v31, -32 +; CHECK-P8-NEXT: li r7, 48 +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 +; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: mr r30, r6 +; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill +; CHECK-P8-NEXT: lvx v31, 0, r5 ; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r30 -; CHECK-P8-NEXT: mr r6, r29 +; CHECK-P8-NEXT: vmr v3, v31 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r28) -; CHECK-P8-NEXT: std r4, 8(r28) -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: li r3, 48 +; CHECK-P8-NEXT: stvx v2, 0, r30 +; CHECK-P8-NEXT: ld r30, 64(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr fp128* nocapture readonly %c, fp128* nocapture %res) { @@ -79,40 +69,31 @@ define void @qpFmadd_02(fp128* nocapture readonly %a, ; CHECK-P8-LABEL: qpFmadd_02: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -80(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r28, -32 -; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r30, -16 -; CHECK-P8-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: ld r7, 0(r5) -; CHECK-P8-NEXT: ld r8, 8(r5) -; CHECK-P8-NEXT: ld r30, 0(r3) -; CHECK-P8-NEXT: ld r29, 8(r3) -; CHECK-P8-NEXT: mr r28, r6 -; CHECK-P8-NEXT: ld r3, 0(r4) -; CHECK-P8-NEXT: ld r4, 8(r4) -; CHECK-P8-NEXT: mr r5, r7 -; CHECK-P8-NEXT: mr r6, r8 +; CHECK-P8-NEXT: .cfi_offset v31, -32 +; CHECK-P8-NEXT: li r7, 48 +; CHECK-P8-NEXT: lvx v2, 0, r4 +; CHECK-P8-NEXT: lvx v3, 0, r5 +; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: mr r30, r6 +; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill +; CHECK-P8-NEXT: lvx v31, 0, r3 ; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r3 -; CHECK-P8-NEXT: mr r6, r4 -; CHECK-P8-NEXT: mr r3, r30 -; CHECK-P8-NEXT: mr r4, r29 +; CHECK-P8-NEXT: vmr v3, v2 +; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r28) -; CHECK-P8-NEXT: std r4, 8(r28) -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: li r3, 48 +; CHECK-P8-NEXT: stvx v2, 0, r30 +; CHECK-P8-NEXT: ld r30, 64(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr fp128* nocapture readonly %b, @@ -149,23 +130,16 @@ define void @qpFmadd_03(fp128* nocapture readonly %a, ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: ld r9, 0(r3) -; CHECK-P8-NEXT: ld r7, 8(r3) -; CHECK-P8-NEXT: ld r8, 0(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: mr r30, r6 -; CHECK-P8-NEXT: ld r6, 8(r4) ; CHECK-P8-NEXT: mr r29, r5 -; CHECK-P8-NEXT: mr r3, r9 -; CHECK-P8-NEXT: mr r4, r7 -; CHECK-P8-NEXT: mr r5, r8 ; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: ld r5, 0(r29) -; CHECK-P8-NEXT: ld r6, 8(r29) +; CHECK-P8-NEXT: lvx v3, 0, r29 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -198,43 +172,37 @@ define void @qpFnmadd(fp128* nocapture readonly %a, ; CHECK-P8-LABEL: qpFnmadd: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -96(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 96 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r28, -32 -; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r30, -16 -; CHECK-P8-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: ld r7, 0(r5) -; CHECK-P8-NEXT: ld r8, 8(r5) -; CHECK-P8-NEXT: ld r30, 0(r3) -; CHECK-P8-NEXT: ld r29, 8(r3) -; CHECK-P8-NEXT: mr r28, r6 -; CHECK-P8-NEXT: ld r3, 0(r4) -; CHECK-P8-NEXT: ld r4, 8(r4) -; CHECK-P8-NEXT: mr r5, r7 -; CHECK-P8-NEXT: mr r6, r8 +; CHECK-P8-NEXT: .cfi_offset v31, -32 +; CHECK-P8-NEXT: li r7, 64 +; CHECK-P8-NEXT: lvx v2, 0, r4 +; CHECK-P8-NEXT: lvx v3, 0, r5 +; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: mr r30, r6 +; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill +; CHECK-P8-NEXT: lvx v31, 0, r3 ; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r3 -; CHECK-P8-NEXT: mr r6, r4 -; CHECK-P8-NEXT: mr r3, r30 -; CHECK-P8-NEXT: mr r4, r29 +; CHECK-P8-NEXT: vmr v3, v2 +; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: li r5, 1 -; CHECK-P8-NEXT: std r3, 0(r28) -; CHECK-P8-NEXT: rldic r5, r5, 63, 0 -; CHECK-P8-NEXT: xor r4, r4, r5 -; CHECK-P8-NEXT: std r4, 8(r28) -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: addi r3, r1, 48 +; CHECK-P8-NEXT: stvx v2, 0, r3 +; CHECK-P8-NEXT: lbz r4, 63(r1) +; CHECK-P8-NEXT: xori r4, r4, 128 +; CHECK-P8-NEXT: stb r4, 63(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: li r3, 64 +; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: stvx v2, 0, r30 +; CHECK-P8-NEXT: ld r30, 80(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: addi r1, r1, 96 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr fp128* nocapture readonly %b, @@ -264,35 +232,31 @@ define void @qpFnmadd_02(fp128* nocapture readonly %a, ; CHECK-P8-LABEL: qpFnmadd_02: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: ld r9, 0(r3) -; CHECK-P8-NEXT: ld r7, 8(r3) -; CHECK-P8-NEXT: ld r8, 0(r4) +; CHECK-P8-NEXT: stdu r1, -80(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: mr r30, r6 -; CHECK-P8-NEXT: ld r6, 8(r4) ; CHECK-P8-NEXT: mr r29, r5 -; CHECK-P8-NEXT: mr r3, r9 -; CHECK-P8-NEXT: mr r4, r7 -; CHECK-P8-NEXT: mr r5, r8 ; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: ld r5, 0(r29) -; CHECK-P8-NEXT: ld r6, 8(r29) +; CHECK-P8-NEXT: lvx v3, 0, r29 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: li r5, 1 -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: rldic r5, r5, 63, 0 -; CHECK-P8-NEXT: xor r4, r4, r5 -; CHECK-P8-NEXT: std r4, 8(r30) -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: addi r3, r1, 32 +; CHECK-P8-NEXT: stvx v2, 0, r3 +; CHECK-P8-NEXT: lbz r4, 47(r1) +; CHECK-P8-NEXT: xori r4, r4, 128 +; CHECK-P8-NEXT: stb r4, 47(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: stvx v2, 0, r30 +; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload @@ -325,40 +289,31 @@ define void @qpFmsub(fp128* nocapture readonly %a, ; CHECK-P8-LABEL: qpFmsub: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -80(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r28, -32 -; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r30, -16 -; CHECK-P8-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: ld r7, 0(r5) -; CHECK-P8-NEXT: ld r8, 8(r5) -; CHECK-P8-NEXT: ld r30, 0(r3) -; CHECK-P8-NEXT: ld r29, 8(r3) -; CHECK-P8-NEXT: mr r28, r6 -; CHECK-P8-NEXT: ld r3, 0(r4) -; CHECK-P8-NEXT: ld r4, 8(r4) -; CHECK-P8-NEXT: mr r5, r7 -; CHECK-P8-NEXT: mr r6, r8 +; CHECK-P8-NEXT: .cfi_offset v31, -32 +; CHECK-P8-NEXT: li r7, 48 +; CHECK-P8-NEXT: lvx v2, 0, r4 +; CHECK-P8-NEXT: lvx v3, 0, r5 +; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: mr r30, r6 +; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill +; CHECK-P8-NEXT: lvx v31, 0, r3 ; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r3 -; CHECK-P8-NEXT: mr r6, r4 -; CHECK-P8-NEXT: mr r3, r30 -; CHECK-P8-NEXT: mr r4, r29 +; CHECK-P8-NEXT: vmr v3, v2 +; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r28) -; CHECK-P8-NEXT: std r4, 8(r28) -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: li r3, 48 +; CHECK-P8-NEXT: stvx v2, 0, r30 +; CHECK-P8-NEXT: ld r30, 64(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr fp128* nocapture readonly %b, @@ -395,23 +350,16 @@ define void @qpFmsub_02(fp128* nocapture readonly %a, ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: ld r9, 0(r3) -; CHECK-P8-NEXT: ld r7, 8(r3) -; CHECK-P8-NEXT: ld r8, 0(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: mr r30, r6 -; CHECK-P8-NEXT: ld r6, 8(r4) ; CHECK-P8-NEXT: mr r29, r5 -; CHECK-P8-NEXT: mr r3, r9 -; CHECK-P8-NEXT: mr r4, r7 -; CHECK-P8-NEXT: mr r5, r8 ; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: ld r5, 0(r29) -; CHECK-P8-NEXT: ld r6, 8(r29) +; CHECK-P8-NEXT: lvx v3, 0, r29 ; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -445,43 +393,37 @@ define void @qpFnmsub(fp128* nocapture readonly %a, ; CHECK-P8-LABEL: qpFnmsub: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -96(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 96 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r28, -32 -; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r30, -16 -; CHECK-P8-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: ld r7, 0(r5) -; CHECK-P8-NEXT: ld r8, 8(r5) -; CHECK-P8-NEXT: ld r30, 0(r3) -; CHECK-P8-NEXT: ld r29, 8(r3) -; CHECK-P8-NEXT: mr r28, r6 -; CHECK-P8-NEXT: ld r3, 0(r4) -; CHECK-P8-NEXT: ld r4, 8(r4) -; CHECK-P8-NEXT: mr r5, r7 -; CHECK-P8-NEXT: mr r6, r8 +; CHECK-P8-NEXT: .cfi_offset v31, -32 +; CHECK-P8-NEXT: li r7, 64 +; CHECK-P8-NEXT: lvx v2, 0, r4 +; CHECK-P8-NEXT: lvx v3, 0, r5 +; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: mr r30, r6 +; CHECK-P8-NEXT: stvx v31, r1, r7 # 16-byte Folded Spill +; CHECK-P8-NEXT: lvx v31, 0, r3 ; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r3 -; CHECK-P8-NEXT: mr r6, r4 -; CHECK-P8-NEXT: mr r3, r30 -; CHECK-P8-NEXT: mr r4, r29 +; CHECK-P8-NEXT: vmr v3, v2 +; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: li r5, 1 -; CHECK-P8-NEXT: std r3, 0(r28) -; CHECK-P8-NEXT: rldic r5, r5, 63, 0 -; CHECK-P8-NEXT: xor r4, r4, r5 -; CHECK-P8-NEXT: std r4, 8(r28) -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: addi r3, r1, 48 +; CHECK-P8-NEXT: stvx v2, 0, r3 +; CHECK-P8-NEXT: lbz r4, 63(r1) +; CHECK-P8-NEXT: xori r4, r4, 128 +; CHECK-P8-NEXT: stb r4, 63(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: li r3, 64 +; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: stvx v2, 0, r30 +; CHECK-P8-NEXT: ld r30, 80(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: addi r1, r1, 96 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr fp128* nocapture readonly %b, @@ -511,35 +453,31 @@ define void @qpFnmsub_02(fp128* nocapture readonly %a, ; CHECK-P8-LABEL: qpFnmsub_02: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: ld r9, 0(r3) -; CHECK-P8-NEXT: ld r7, 8(r3) -; CHECK-P8-NEXT: ld r8, 0(r4) +; CHECK-P8-NEXT: stdu r1, -80(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: mr r30, r6 -; CHECK-P8-NEXT: ld r6, 8(r4) ; CHECK-P8-NEXT: mr r29, r5 -; CHECK-P8-NEXT: mr r3, r9 -; CHECK-P8-NEXT: mr r4, r7 -; CHECK-P8-NEXT: mr r5, r8 ; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: ld r5, 0(r29) -; CHECK-P8-NEXT: ld r6, 8(r29) +; CHECK-P8-NEXT: lvx v3, 0, r29 ; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: li r5, 1 -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: rldic r5, r5, 63, 0 -; CHECK-P8-NEXT: xor r4, r4, r5 -; CHECK-P8-NEXT: std r4, 8(r30) -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: addi r3, r1, 32 +; CHECK-P8-NEXT: stvx v2, 0, r3 +; CHECK-P8-NEXT: lbz r4, 47(r1) +; CHECK-P8-NEXT: xori r4, r4, 128 +; CHECK-P8-NEXT: stb r4, 47(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: stvx v2, 0, r30 +; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll index 3acfc5bcf0c4..5c17dda209e9 100644 --- a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll +++ b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll @@ -16,10 +16,9 @@ define fp128 @loadConstant() { ; ; CHECK-P8-LABEL: loadConstant: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: lis r3, 1 -; CHECK-P8-NEXT: ori r3, r3, 5 -; CHECK-P8-NEXT: rldic r4, r3, 46, 1 -; CHECK-P8-NEXT: li r3, 0 +; CHECK-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha +; CHECK-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: blr entry: ret fp128 0xL00000000000000004001400000000000 @@ -45,10 +44,9 @@ define fp128 @loadConstant2(fp128 %a, fp128 %b) { ; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: lis r5, 1 -; CHECK-P8-NEXT: ori r5, r5, 5 -; CHECK-P8-NEXT: rldic r6, r5, 46, 1 -; CHECK-P8-NEXT: li r5, 0 +; CHECK-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha +; CHECK-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l +; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -136,12 +134,10 @@ define fp128 @fp128Array(fp128* nocapture readonly %farray, ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: sldi r4, r4, 4 -; CHECK-P8-NEXT: ld r7, 0(r3) -; CHECK-P8-NEXT: add r6, r3, r4 -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: ld r5, -16(r6) -; CHECK-P8-NEXT: ld r6, -8(r6) -; CHECK-P8-NEXT: mr r3, r7 +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: add r4, r3, r4 +; CHECK-P8-NEXT: addi r4, r4, -16 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -183,139 +179,115 @@ define fp128 @maxVecParam(fp128 %p1, fp128 %p2, fp128 %p3, fp128 %p4, fp128 %p5, ; CHECK-P8-LABEL: maxVecParam: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 208 -; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r14, -144 -; CHECK-P8-NEXT: .cfi_offset r15, -136 -; CHECK-P8-NEXT: .cfi_offset r16, -128 -; CHECK-P8-NEXT: .cfi_offset r17, -120 -; CHECK-P8-NEXT: .cfi_offset r18, -112 -; CHECK-P8-NEXT: .cfi_offset r19, -104 -; CHECK-P8-NEXT: .cfi_offset r20, -96 -; CHECK-P8-NEXT: .cfi_offset r21, -88 -; CHECK-P8-NEXT: .cfi_offset r22, -80 -; CHECK-P8-NEXT: .cfi_offset r23, -72 -; CHECK-P8-NEXT: .cfi_offset r24, -64 -; CHECK-P8-NEXT: .cfi_offset r25, -56 -; CHECK-P8-NEXT: .cfi_offset r26, -48 -; CHECK-P8-NEXT: .cfi_offset r27, -40 -; CHECK-P8-NEXT: .cfi_offset r28, -32 -; CHECK-P8-NEXT: .cfi_offset r29, -24 -; CHECK-P8-NEXT: .cfi_offset r30, -16 -; CHECK-P8-NEXT: .cfi_offset r31, -8 -; CHECK-P8-NEXT: std r14, -144(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r15, -136(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r16, -128(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r17, -120(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r18, -112(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r19, -104(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r20, -96(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r21, -88(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r22, -80(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r23, -72(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r24, -64(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r25, -56(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r26, -48(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r27, -40(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r31, -8(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -208(r1) -; CHECK-P8-NEXT: mr r17, r7 -; CHECK-P8-NEXT: ld r7, 432(r1) -; CHECK-P8-NEXT: ld r26, 400(r1) -; CHECK-P8-NEXT: ld r25, 408(r1) -; CHECK-P8-NEXT: ld r24, 384(r1) -; CHECK-P8-NEXT: mr r20, r10 -; CHECK-P8-NEXT: ld r23, 392(r1) -; CHECK-P8-NEXT: ld r22, 368(r1) -; CHECK-P8-NEXT: ld r21, 376(r1) -; CHECK-P8-NEXT: ld r16, 352(r1) -; CHECK-P8-NEXT: mr r19, r9 -; CHECK-P8-NEXT: mr r18, r8 -; CHECK-P8-NEXT: ld r15, 360(r1) -; CHECK-P8-NEXT: ld r14, 336(r1) -; CHECK-P8-NEXT: ld r31, 344(r1) -; CHECK-P8-NEXT: ld r30, 320(r1) -; CHECK-P8-NEXT: std r7, 56(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: ld r7, 440(r1) -; CHECK-P8-NEXT: ld r29, 328(r1) -; CHECK-P8-NEXT: ld r28, 304(r1) -; CHECK-P8-NEXT: ld r27, 312(r1) -; CHECK-P8-NEXT: std r7, 48(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: ld r7, 416(r1) -; CHECK-P8-NEXT: std r7, 40(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: ld r7, 424(r1) -; CHECK-P8-NEXT: std r7, 32(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: stdu r1, -224(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 224 +; CHECK-P8-NEXT: .cfi_offset lr, 16 +; CHECK-P8-NEXT: .cfi_offset v21, -176 +; CHECK-P8-NEXT: .cfi_offset v22, -160 +; CHECK-P8-NEXT: .cfi_offset v23, -144 +; CHECK-P8-NEXT: .cfi_offset v24, -128 +; CHECK-P8-NEXT: .cfi_offset v25, -112 +; CHECK-P8-NEXT: .cfi_offset v26, -96 +; CHECK-P8-NEXT: .cfi_offset v27, -80 +; CHECK-P8-NEXT: .cfi_offset v28, -64 +; CHECK-P8-NEXT: .cfi_offset v29, -48 +; CHECK-P8-NEXT: .cfi_offset v30, -32 +; CHECK-P8-NEXT: .cfi_offset v31, -16 +; CHECK-P8-NEXT: li r3, 48 +; CHECK-P8-NEXT: stvx v21, r1, r3 # 16-byte Folded Spill +; CHECK-P8-NEXT: li r3, 64 +; CHECK-P8-NEXT: vmr v21, v4 +; CHECK-P8-NEXT: stvx v22, r1, r3 # 16-byte Folded Spill +; CHECK-P8-NEXT: li r3, 80 +; CHECK-P8-NEXT: vmr v22, v5 +; CHECK-P8-NEXT: stvx v23, r1, r3 # 16-byte Folded Spill +; CHECK-P8-NEXT: li r3, 96 +; CHECK-P8-NEXT: vmr v23, v6 +; CHECK-P8-NEXT: stvx v24, r1, r3 # 16-byte Folded Spill +; CHECK-P8-NEXT: li r3, 112 +; CHECK-P8-NEXT: vmr v24, v7 +; CHECK-P8-NEXT: stvx v25, r1, r3 # 16-byte Folded Spill +; CHECK-P8-NEXT: li r3, 128 +; CHECK-P8-NEXT: vmr v25, v8 +; CHECK-P8-NEXT: stvx v26, r1, r3 # 16-byte Folded Spill +; CHECK-P8-NEXT: li r3, 144 +; CHECK-P8-NEXT: vmr v26, v9 +; CHECK-P8-NEXT: stvx v27, r1, r3 # 16-byte Folded Spill +; CHECK-P8-NEXT: li r3, 160 +; CHECK-P8-NEXT: vmr v27, v10 +; CHECK-P8-NEXT: stvx v28, r1, r3 # 16-byte Folded Spill +; CHECK-P8-NEXT: li r3, 176 +; CHECK-P8-NEXT: vmr v28, v11 +; CHECK-P8-NEXT: stvx v29, r1, r3 # 16-byte Folded Spill +; CHECK-P8-NEXT: li r3, 192 +; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill +; CHECK-P8-NEXT: li r3, 208 +; CHECK-P8-NEXT: vmr v30, v12 +; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill +; CHECK-P8-NEXT: addi r3, r1, 448 +; CHECK-P8-NEXT: vmr v31, v13 +; CHECK-P8-NEXT: lvx v29, 0, r3 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r17 -; CHECK-P8-NEXT: mr r6, r18 +; CHECK-P8-NEXT: vmr v3, v21 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r19 -; CHECK-P8-NEXT: mr r6, r20 +; CHECK-P8-NEXT: vmr v3, v22 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r28 -; CHECK-P8-NEXT: mr r6, r27 +; CHECK-P8-NEXT: vmr v3, v23 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r30 -; CHECK-P8-NEXT: mr r6, r29 +; CHECK-P8-NEXT: vmr v3, v24 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r14 -; CHECK-P8-NEXT: mr r6, r31 +; CHECK-P8-NEXT: vmr v3, v25 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r16 -; CHECK-P8-NEXT: mr r6, r15 +; CHECK-P8-NEXT: vmr v3, v26 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r22 -; CHECK-P8-NEXT: mr r6, r21 +; CHECK-P8-NEXT: vmr v3, v27 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r24 -; CHECK-P8-NEXT: mr r6, r23 +; CHECK-P8-NEXT: vmr v3, v28 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r26 -; CHECK-P8-NEXT: mr r6, r25 +; CHECK-P8-NEXT: vmr v3, v30 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: ld r5, 40(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r6, 32(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: vmr v3, v31 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: ld r5, 56(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r6, 48(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: vmr v3, v29 ; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: addi r1, r1, 208 +; CHECK-P8-NEXT: li r3, 208 +; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: li r3, 192 +; CHECK-P8-NEXT: lvx v30, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: li r3, 176 +; CHECK-P8-NEXT: lvx v29, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: li r3, 160 +; CHECK-P8-NEXT: lvx v28, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: li r3, 144 +; CHECK-P8-NEXT: lvx v27, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: li r3, 128 +; CHECK-P8-NEXT: lvx v26, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: li r3, 112 +; CHECK-P8-NEXT: lvx v25, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: li r3, 96 +; CHECK-P8-NEXT: lvx v24, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: li r3, 80 +; CHECK-P8-NEXT: lvx v23, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: li r3, 64 +; CHECK-P8-NEXT: lvx v22, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: li r3, 48 +; CHECK-P8-NEXT: lvx v21, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: addi r1, r1, 224 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: ld r31, -8(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r27, -40(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r26, -48(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r25, -56(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r24, -64(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r23, -72(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r22, -80(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r21, -88(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 -; CHECK-P8-NEXT: ld r20, -96(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r19, -104(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r18, -112(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r17, -120(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r16, -128(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r15, -136(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r14, -144(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: blr fp128 %p6, fp128 %p7, fp128 %p8, fp128 %p9, fp128 %p10, fp128 %p11, fp128 %p12, fp128 %p13) { @@ -349,37 +321,31 @@ define fp128 @mixParam_01(fp128 %a, i32 signext %i, fp128 %b) { ; CHECK-P8-LABEL: mixParam_01: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -80(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r28, -32 -; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r30, -16 -; CHECK-P8-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -64(r1) +; CHECK-P8-NEXT: .cfi_offset v31, -32 +; CHECK-P8-NEXT: li r3, 48 +; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: mr r30, r5 -; CHECK-P8-NEXT: mr r5, r6 -; CHECK-P8-NEXT: mr r6, r7 +; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r3, r30 -; CHECK-P8-NEXT: mr r28, r4 +; CHECK-P8-NEXT: vmr v31, v2 ; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r3 -; CHECK-P8-NEXT: mr r6, r4 -; CHECK-P8-NEXT: mr r3, r29 -; CHECK-P8-NEXT: mr r4, r28 +; CHECK-P8-NEXT: vmr v3, v2 +; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: li r3, 48 +; CHECK-P8-NEXT: ld r30, 64(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr entry: @@ -401,37 +367,31 @@ define fastcc fp128 @mixParam_01f(fp128 %a, i32 signext %i, fp128 %b) { ; CHECK-P8-LABEL: mixParam_01f: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -80(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r28, -32 -; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r30, -16 -; CHECK-P8-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: mr r30, r5 -; CHECK-P8-NEXT: mr r5, r6 -; CHECK-P8-NEXT: mr r6, r7 +; CHECK-P8-NEXT: .cfi_offset v31, -32 +; CHECK-P8-NEXT: li r4, 48 +; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: mr r30, r3 +; CHECK-P8-NEXT: stvx v31, r1, r4 # 16-byte Folded Spill ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r3, r30 -; CHECK-P8-NEXT: mr r28, r4 +; CHECK-P8-NEXT: vmr v31, v2 ; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r3 -; CHECK-P8-NEXT: mr r6, r4 -; CHECK-P8-NEXT: mr r3, r29 -; CHECK-P8-NEXT: mr r4, r28 +; CHECK-P8-NEXT: vmr v3, v2 +; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: li r3, 48 +; CHECK-P8-NEXT: ld r30, 64(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr entry: @@ -461,48 +421,41 @@ define fp128 @mixParam_02(fp128 %p1, double %p2, i64* nocapture %p3, ; CHECK-P8-LABEL: mixParam_02: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -80(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r29, -32 -; CHECK-P8-NEXT: .cfi_offset r30, -24 ; CHECK-P8-NEXT: .cfi_offset f31, -8 -; CHECK-P8-NEXT: std r29, -32(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r30, -24(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: mr r11, r4 -; CHECK-P8-NEXT: lwz r4, 160(r1) -; CHECK-P8-NEXT: add r5, r7, r9 +; CHECK-P8-NEXT: .cfi_offset v31, -32 +; CHECK-P8-NEXT: li r3, 48 +; CHECK-P8-NEXT: add r4, r7, r9 +; CHECK-P8-NEXT: vmr v4, v2 +; CHECK-P8-NEXT: stfd f31, 72(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill +; CHECK-P8-NEXT: lwz r3, 176(r1) +; CHECK-P8-NEXT: add r4, r4, r10 ; CHECK-P8-NEXT: fmr f31, f1 -; CHECK-P8-NEXT: add r5, r5, r10 -; CHECK-P8-NEXT: add r4, r5, r4 -; CHECK-P8-NEXT: clrldi r4, r4, 32 -; CHECK-P8-NEXT: std r4, 0(r6) -; CHECK-P8-NEXT: mr r6, r3 -; CHECK-P8-NEXT: ld r5, 0(r8) -; CHECK-P8-NEXT: ld r4, 8(r8) -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r5, r6 -; CHECK-P8-NEXT: mr r6, r11 +; CHECK-P8-NEXT: add r3, r4, r3 +; CHECK-P8-NEXT: clrldi r3, r3, 32 +; CHECK-P8-NEXT: std r3, 0(r6) +; CHECK-P8-NEXT: lvx v3, 0, r8 +; CHECK-P8-NEXT: vmr v2, v3 +; CHECK-P8-NEXT: vmr v3, v4 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: fmr f1, f31 -; CHECK-P8-NEXT: mr r30, r3 -; CHECK-P8-NEXT: mr r29, r4 +; CHECK-P8-NEXT: vmr v31, v2 ; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r3 -; CHECK-P8-NEXT: mr r6, r4 -; CHECK-P8-NEXT: mr r3, r30 -; CHECK-P8-NEXT: mr r4, r29 +; CHECK-P8-NEXT: vmr v3, v2 +; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: li r3, 48 +; CHECK-P8-NEXT: lfd f31, 72(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r30, -24(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r29, -32(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr i16 signext %p4, fp128* nocapture readonly %p5, @@ -541,47 +494,40 @@ define fastcc fp128 @mixParam_02f(fp128 %p1, double %p2, i64* nocapture %p3, ; CHECK-P8-LABEL: mixParam_02f: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -80(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r29, -32 -; CHECK-P8-NEXT: .cfi_offset r30, -24 ; CHECK-P8-NEXT: .cfi_offset f31, -8 -; CHECK-P8-NEXT: std r29, -32(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r30, -24(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: mr r11, r4 -; CHECK-P8-NEXT: add r4, r6, r8 -; CHECK-P8-NEXT: mr r6, r3 +; CHECK-P8-NEXT: .cfi_offset v31, -32 +; CHECK-P8-NEXT: add r4, r4, r6 +; CHECK-P8-NEXT: vmr v4, v2 +; CHECK-P8-NEXT: li r9, 48 +; CHECK-P8-NEXT: stfd f31, 72(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: add r4, r4, r7 +; CHECK-P8-NEXT: stvx v31, r1, r9 # 16-byte Folded Spill ; CHECK-P8-NEXT: fmr f31, f1 -; CHECK-P8-NEXT: add r4, r4, r9 -; CHECK-P8-NEXT: add r4, r4, r10 +; CHECK-P8-NEXT: add r4, r4, r8 ; CHECK-P8-NEXT: clrldi r4, r4, 32 -; CHECK-P8-NEXT: std r4, 0(r5) -; CHECK-P8-NEXT: ld r5, 0(r7) -; CHECK-P8-NEXT: ld r4, 8(r7) -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r5, r6 -; CHECK-P8-NEXT: mr r6, r11 +; CHECK-P8-NEXT: std r4, 0(r3) +; CHECK-P8-NEXT: lvx v3, 0, r5 +; CHECK-P8-NEXT: vmr v2, v3 +; CHECK-P8-NEXT: vmr v3, v4 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: fmr f1, f31 -; CHECK-P8-NEXT: mr r30, r3 -; CHECK-P8-NEXT: mr r29, r4 +; CHECK-P8-NEXT: vmr v31, v2 ; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r3 -; CHECK-P8-NEXT: mr r6, r4 -; CHECK-P8-NEXT: mr r3, r30 -; CHECK-P8-NEXT: mr r4, r29 +; CHECK-P8-NEXT: vmr v3, v2 +; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: li r3, 48 +; CHECK-P8-NEXT: lfd f31, 72(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r30, -24(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r29, -32(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr i16 signext %p4, fp128* nocapture readonly %p5, @@ -620,40 +566,35 @@ define void @mixParam_03(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1, ; CHECK-P8-LABEL: mixParam_03: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -80(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r28, -32 -; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r30, -16 -; CHECK-P8-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: ld r6, 168(r1) -; CHECK-P8-NEXT: std r4, 8(r9) -; CHECK-P8-NEXT: std r3, 0(r9) +; CHECK-P8-NEXT: .cfi_offset v31, -32 +; CHECK-P8-NEXT: ld r4, 184(r1) +; CHECK-P8-NEXT: li r3, 48 +; CHECK-P8-NEXT: stvx v2, 0, r9 +; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: mr r30, r5 +; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: mr r3, r10 -; CHECK-P8-NEXT: mr r28, r5 -; CHECK-P8-NEXT: stvx v2, 0, r6 -; CHECK-P8-NEXT: ld r30, 0(r9) -; CHECK-P8-NEXT: ld r29, 8(r9) +; CHECK-P8-NEXT: stvx v3, 0, r4 +; CHECK-P8-NEXT: lvx v31, 0, r9 ; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r3 -; CHECK-P8-NEXT: mr r6, r4 -; CHECK-P8-NEXT: mr r3, r30 -; CHECK-P8-NEXT: mr r4, r29 +; CHECK-P8-NEXT: vmr v3, v2 +; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: stfdx f1, 0, r28 -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: li r3, 48 +; CHECK-P8-NEXT: stfdx f1, 0, r30 +; CHECK-P8-NEXT: ld r30, 64(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1, @@ -686,39 +627,34 @@ define fastcc void @mixParam_03f(fp128 %f1, double* nocapture %d1, <4 x i32> %ve ; CHECK-P8-LABEL: mixParam_03f: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: std r0, 16(r1) +; CHECK-P8-NEXT: stdu r1, -80(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r28, -32 -; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r30, -16 -; CHECK-P8-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: std r4, 8(r6) -; CHECK-P8-NEXT: std r3, 0(r6) -; CHECK-P8-NEXT: mr r3, r7 -; CHECK-P8-NEXT: mr r28, r5 -; CHECK-P8-NEXT: stvx v2, 0, r9 -; CHECK-P8-NEXT: ld r30, 0(r6) -; CHECK-P8-NEXT: ld r29, 8(r6) +; CHECK-P8-NEXT: .cfi_offset v31, -32 +; CHECK-P8-NEXT: li r6, 48 +; CHECK-P8-NEXT: stvx v2, 0, r4 +; CHECK-P8-NEXT: stvx v3, 0, r7 +; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill +; CHECK-P8-NEXT: mr r30, r3 +; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: stvx v31, r1, r6 # 16-byte Folded Spill +; CHECK-P8-NEXT: lvx v31, 0, r4 ; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: mr r5, r3 -; CHECK-P8-NEXT: mr r6, r4 -; CHECK-P8-NEXT: mr r3, r30 -; CHECK-P8-NEXT: mr r4, r29 +; CHECK-P8-NEXT: vmr v3, v2 +; CHECK-P8-NEXT: vmr v2, v31 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: stfdx f1, 0, r28 -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: li r3, 48 +; CHECK-P8-NEXT: stfdx f1, 0, r30 +; CHECK-P8-NEXT: ld r30, 64(r1) # 8-byte Folded Reload +; CHECK-P8-NEXT: lvx v31, r1, r3 # 16-byte Folded Reload +; CHECK-P8-NEXT: addi r1, r1, 80 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1, @@ -757,15 +693,15 @@ define signext i32 @noopt_call_crash() #0 { ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -32(r1) -; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 +; CHECK-P8-NEXT: stdu r1, -96(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 96 ; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: bl in ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl out ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: li r3, 0 -; CHECK-P8-NEXT: addi r1, r1, 32 +; CHECK-P8-NEXT: addi r1, r1, 96 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/f128-rounding.ll b/llvm/test/CodeGen/PowerPC/f128-rounding.ll index d75bd15aa532..2913635408b4 100644 --- a/llvm/test/CodeGen/PowerPC/f128-rounding.ll +++ b/llvm/test/CodeGen/PowerPC/f128-rounding.ll @@ -2,7 +2,7 @@ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \ -; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -enable-soft-fp128 | FileCheck %s \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ ; RUN: -check-prefix=CHECK-P8 define void @qp_trunc(fp128* nocapture readonly %a, fp128* nocapture %res) { diff --git a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll index cf9f48f5b47b..32b0f10def29 100644 --- a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll +++ b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll @@ -28,9 +28,7 @@ define i64 @qpConv2sdw(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl __fixkfdi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -67,9 +65,8 @@ define void @qpConv2sdw_02(i64* nocapture %res) local_unnamed_addr #1 { ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r5, 32(r4) -; CHECK-P8-NEXT: ld r4, 40(r4) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: addi r4, r4, 32 +; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: bl __fixkfdi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: std r3, 0(r30) @@ -109,12 +106,10 @@ define i64 @qpConv2sdw_03(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-P8-NEXT: ld r7, 0(r3) -; CHECK-P8-NEXT: ld r6, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r7 -; CHECK-P8-NEXT: ld r5, 16(r6) -; CHECK-P8-NEXT: ld r6, 24(r6) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-P8-NEXT: addi r4, r4, 16 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixkfdi @@ -154,14 +149,9 @@ define void @qpConv2sdw_04(fp128* nocapture readonly %a, ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r9, 0(r3) -; CHECK-P8-NEXT: ld r7, 8(r3) -; CHECK-P8-NEXT: ld r8, 0(r4) -; CHECK-P8-NEXT: ld r6, 8(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: mr r30, r5 -; CHECK-P8-NEXT: mr r3, r9 -; CHECK-P8-NEXT: mr r4, r7 -; CHECK-P8-NEXT: mr r5, r8 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixkfdi @@ -210,9 +200,8 @@ define void @qpConv2sdw_testXForm(i64* nocapture %res, i32 signext %idx) { ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r5, 32(r4) -; CHECK-P8-NEXT: ld r4, 40(r4) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: addi r4, r4, 32 +; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: bl __fixkfdi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: sldi r4, r30, 3 @@ -251,9 +240,7 @@ define i64 @qpConv2udw(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl __fixunskfdi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -290,9 +277,8 @@ define void @qpConv2udw_02(i64* nocapture %res) { ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r5, 32(r4) -; CHECK-P8-NEXT: ld r4, 40(r4) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: addi r4, r4, 32 +; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: bl __fixunskfdi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: std r3, 0(r30) @@ -332,12 +318,10 @@ define i64 @qpConv2udw_03(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-P8-NEXT: ld r7, 0(r3) -; CHECK-P8-NEXT: ld r6, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r7 -; CHECK-P8-NEXT: ld r5, 16(r6) -; CHECK-P8-NEXT: ld r6, 24(r6) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-P8-NEXT: addi r4, r4, 16 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixunskfdi @@ -377,14 +361,9 @@ define void @qpConv2udw_04(fp128* nocapture readonly %a, ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r9, 0(r3) -; CHECK-P8-NEXT: ld r7, 8(r3) -; CHECK-P8-NEXT: ld r8, 0(r4) -; CHECK-P8-NEXT: ld r6, 8(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: mr r30, r5 -; CHECK-P8-NEXT: mr r3, r9 -; CHECK-P8-NEXT: mr r4, r7 -; CHECK-P8-NEXT: mr r5, r8 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixunskfdi @@ -433,9 +412,7 @@ define void @qpConv2udw_testXForm(i64* nocapture %res, i32 signext %idx) { ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r5, 0(r4) -; CHECK-P8-NEXT: ld r4, 8(r4) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: bl __fixunskfdi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: sldi r4, r30, 3 @@ -475,9 +452,7 @@ define signext i32 @qpConv2sw(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: extsw r3, r3 @@ -515,9 +490,8 @@ define void @qpConv2sw_02(i32* nocapture %res) { ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r5, 32(r4) -; CHECK-P8-NEXT: ld r4, 40(r4) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: addi r4, r4, 32 +; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: stw r3, 0(r30) @@ -558,12 +532,10 @@ define signext i32 @qpConv2sw_03(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-P8-NEXT: ld r7, 0(r3) -; CHECK-P8-NEXT: ld r6, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r7 -; CHECK-P8-NEXT: ld r5, 16(r6) -; CHECK-P8-NEXT: ld r6, 24(r6) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-P8-NEXT: addi r4, r4, 16 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixkfsi @@ -604,14 +576,9 @@ define void @qpConv2sw_04(fp128* nocapture readonly %a, ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r9, 0(r3) -; CHECK-P8-NEXT: ld r7, 8(r3) -; CHECK-P8-NEXT: ld r8, 0(r4) -; CHECK-P8-NEXT: ld r6, 8(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: mr r30, r5 -; CHECK-P8-NEXT: mr r3, r9 -; CHECK-P8-NEXT: mr r4, r7 -; CHECK-P8-NEXT: mr r5, r8 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixkfsi @@ -650,9 +617,7 @@ define zeroext i32 @qpConv2uw(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl __fixunskfsi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -689,9 +654,8 @@ define void @qpConv2uw_02(i32* nocapture %res) { ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r5, 32(r4) -; CHECK-P8-NEXT: ld r4, 40(r4) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: addi r4, r4, 32 +; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: bl __fixunskfsi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: stw r3, 0(r30) @@ -732,12 +696,10 @@ define zeroext i32 @qpConv2uw_03(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-P8-NEXT: ld r7, 0(r3) -; CHECK-P8-NEXT: ld r6, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r7 -; CHECK-P8-NEXT: ld r5, 16(r6) -; CHECK-P8-NEXT: ld r6, 24(r6) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-P8-NEXT: addi r4, r4, 16 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixunskfsi @@ -777,14 +739,9 @@ define void @qpConv2uw_04(fp128* nocapture readonly %a, ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r9, 0(r3) -; CHECK-P8-NEXT: ld r7, 8(r3) -; CHECK-P8-NEXT: ld r8, 0(r4) -; CHECK-P8-NEXT: ld r6, 8(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: mr r30, r5 -; CHECK-P8-NEXT: mr r3, r9 -; CHECK-P8-NEXT: mr r4, r7 -; CHECK-P8-NEXT: mr r5, r8 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixunskfsi @@ -824,9 +781,7 @@ define signext i16 @qpConv2shw(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: extsw r3, r3 @@ -863,9 +818,8 @@ define void @qpConv2shw_02(i16* nocapture %res) { ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r5, 32(r4) -; CHECK-P8-NEXT: ld r4, 40(r4) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: addi r4, r4, 32 +; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: sth r3, 0(r30) @@ -905,12 +859,10 @@ define signext i16 @qpConv2shw_03(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-P8-NEXT: ld r7, 0(r3) -; CHECK-P8-NEXT: ld r6, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r7 -; CHECK-P8-NEXT: ld r5, 16(r6) -; CHECK-P8-NEXT: ld r6, 24(r6) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-P8-NEXT: addi r4, r4, 16 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixkfsi @@ -950,14 +902,9 @@ define void @qpConv2shw_04(fp128* nocapture readonly %a, ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r9, 0(r3) -; CHECK-P8-NEXT: ld r7, 8(r3) -; CHECK-P8-NEXT: ld r8, 0(r4) -; CHECK-P8-NEXT: ld r6, 8(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: mr r30, r5 -; CHECK-P8-NEXT: mr r3, r9 -; CHECK-P8-NEXT: mr r4, r7 -; CHECK-P8-NEXT: mr r5, r8 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixkfsi @@ -995,9 +942,7 @@ define zeroext i16 @qpConv2uhw(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -1033,9 +978,8 @@ define void @qpConv2uhw_02(i16* nocapture %res) { ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r5, 32(r4) -; CHECK-P8-NEXT: ld r4, 40(r4) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: addi r4, r4, 32 +; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: sth r3, 0(r30) @@ -1075,12 +1019,10 @@ define zeroext i16 @qpConv2uhw_03(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-P8-NEXT: ld r7, 0(r3) -; CHECK-P8-NEXT: ld r6, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r7 -; CHECK-P8-NEXT: ld r5, 16(r6) -; CHECK-P8-NEXT: ld r6, 24(r6) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-P8-NEXT: addi r4, r4, 16 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixkfsi @@ -1119,14 +1061,9 @@ define void @qpConv2uhw_04(fp128* nocapture readonly %a, ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r9, 0(r3) -; CHECK-P8-NEXT: ld r7, 8(r3) -; CHECK-P8-NEXT: ld r8, 0(r4) -; CHECK-P8-NEXT: ld r6, 8(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: mr r30, r5 -; CHECK-P8-NEXT: mr r3, r9 -; CHECK-P8-NEXT: mr r4, r7 -; CHECK-P8-NEXT: mr r5, r8 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixkfsi @@ -1164,9 +1101,7 @@ define signext i8 @qpConv2sb(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: extsw r3, r3 @@ -1203,9 +1138,8 @@ define void @qpConv2sb_02(i8* nocapture %res) { ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r5, 32(r4) -; CHECK-P8-NEXT: ld r4, 40(r4) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: addi r4, r4, 32 +; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: stb r3, 0(r30) @@ -1245,12 +1179,10 @@ define signext i8 @qpConv2sb_03(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-P8-NEXT: ld r7, 0(r3) -; CHECK-P8-NEXT: ld r6, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r7 -; CHECK-P8-NEXT: ld r5, 16(r6) -; CHECK-P8-NEXT: ld r6, 24(r6) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-P8-NEXT: addi r4, r4, 16 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixkfsi @@ -1290,14 +1222,9 @@ define void @qpConv2sb_04(fp128* nocapture readonly %a, ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r9, 0(r3) -; CHECK-P8-NEXT: ld r7, 8(r3) -; CHECK-P8-NEXT: ld r8, 0(r4) -; CHECK-P8-NEXT: ld r6, 8(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: mr r30, r5 -; CHECK-P8-NEXT: mr r3, r9 -; CHECK-P8-NEXT: mr r4, r7 -; CHECK-P8-NEXT: mr r5, r8 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixkfsi @@ -1335,9 +1262,7 @@ define zeroext i8 @qpConv2ub(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -1373,9 +1298,8 @@ define void @qpConv2ub_02(i8* nocapture %res) { ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r5, 32(r4) -; CHECK-P8-NEXT: ld r4, 40(r4) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: addi r4, r4, 32 +; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: stb r3, 0(r30) @@ -1415,12 +1339,10 @@ define zeroext i8 @qpConv2ub_03(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-P8-NEXT: ld r7, 0(r3) -; CHECK-P8-NEXT: ld r6, .LC0@toc@l(r4) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r7 -; CHECK-P8-NEXT: ld r5, 16(r6) -; CHECK-P8-NEXT: ld r6, 24(r6) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-P8-NEXT: addi r4, r4, 16 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixkfsi @@ -1459,14 +1381,9 @@ define void @qpConv2ub_04(fp128* nocapture readonly %a, ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r9, 0(r3) -; CHECK-P8-NEXT: ld r7, 8(r3) -; CHECK-P8-NEXT: ld r8, 0(r4) -; CHECK-P8-NEXT: ld r6, 8(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: mr r30, r5 -; CHECK-P8-NEXT: mr r3, r9 -; CHECK-P8-NEXT: mr r4, r7 -; CHECK-P8-NEXT: mr r5, r8 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __fixkfsi diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll index e647ebdef224..0e7ec05ffedb 100644 --- a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll +++ b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll @@ -6,7 +6,7 @@ ; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s \ ; RUN: -check-prefix=P9 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ -; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -enable-soft-fp128 -mattr=-vsx \ +; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx \ ; RUN: | FileCheck %s -check-prefix=NOVSX declare i1 @llvm.experimental.constrained.fptosi.i1.f128(fp128, metadata) @@ -183,7 +183,7 @@ define i1 @q_to_u1(fp128 %m) #0 { ; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_offset lr, 16 -; P8-NEXT: bl __fixunskfsi +; P8-NEXT: bl __fixkfsi ; P8-NEXT: nop ; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: ld r0, 16(r1) @@ -203,7 +203,7 @@ define i1 @q_to_u1(fp128 %m) #0 { ; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_offset lr, 16 -; NOVSX-NEXT: bl __fixkfsi +; NOVSX-NEXT: bl __fixunskfsi ; NOVSX-NEXT: nop ; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: ld r0, 16(r1) @@ -786,7 +786,7 @@ define fp128 @u1_to_q(i1 zeroext %m) #0 { ; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_offset lr, 16 -; P8-NEXT: bl __floatunsikf +; P8-NEXT: bl __floatsikf ; P8-NEXT: nop ; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: ld r0, 16(r1) @@ -806,7 +806,7 @@ define fp128 @u1_to_q(i1 zeroext %m) #0 { ; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_offset lr, 16 -; NOVSX-NEXT: bl __floatsikf +; NOVSX-NEXT: bl __floatunsikf ; NOVSX-NEXT: nop ; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: ld r0, 16(r1) diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-f128.ll b/llvm/test/CodeGen/PowerPC/fp-strict-f128.ll index ff165fd6ced6..e2c29f30cd3d 100644 --- a/llvm/test/CodeGen/PowerPC/fp-strict-f128.ll +++ b/llvm/test/CodeGen/PowerPC/fp-strict-f128.ll @@ -154,15 +154,18 @@ define fp128 @fmsub_f128(fp128 %f0, fp128 %f1, fp128 %f2) #0 { ; CHECK-P8: # %bb.0: ; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -32(r1) -; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 +; CHECK-P8-NEXT: stdu r1, -48(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: li r9, 1 -; CHECK-P8-NEXT: rldic r9, r9, 63, 0 -; CHECK-P8-NEXT: xor r8, r8, r9 +; CHECK-P8-NEXT: addi r3, r1, 32 +; CHECK-P8-NEXT: stvx v4, 0, r3 +; CHECK-P8-NEXT: lbz r4, 47(r1) +; CHECK-P8-NEXT: xori r4, r4, 128 +; CHECK-P8-NEXT: stb r4, 47(r1) +; CHECK-P8-NEXT: lvx v4, 0, r3 ; CHECK-P8-NEXT: bl fmaf128 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: addi r1, r1, 32 +; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr @@ -185,15 +188,18 @@ define fp128 @fnmadd_f128(fp128 %f0, fp128 %f1, fp128 %f2) #0 { ; CHECK-P8: # %bb.0: ; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -32(r1) -; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 +; CHECK-P8-NEXT: stdu r1, -48(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: bl fmaf128 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: li r5, 1 -; CHECK-P8-NEXT: rldic r5, r5, 63, 0 -; CHECK-P8-NEXT: xor r4, r4, r5 -; CHECK-P8-NEXT: addi r1, r1, 32 +; CHECK-P8-NEXT: addi r3, r1, 32 +; CHECK-P8-NEXT: stvx v2, 0, r3 +; CHECK-P8-NEXT: lbz r4, 47(r1) +; CHECK-P8-NEXT: xori r4, r4, 128 +; CHECK-P8-NEXT: stb r4, 47(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr @@ -215,21 +221,26 @@ define fp128 @fnmsub_f128(fp128 %f0, fp128 %f1, fp128 %f2) #0 { ; CHECK-P8-LABEL: fnmsub_f128: ; CHECK-P8: # %bb.0: ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 -; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r30, -16 -; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) -; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: li r9, 1 -; CHECK-P8-NEXT: rldic r30, r9, 63, 0 -; CHECK-P8-NEXT: xor r8, r8, r30 +; CHECK-P8-NEXT: stdu r1, -64(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: .cfi_offset lr, 16 +; CHECK-P8-NEXT: addi r3, r1, 32 +; CHECK-P8-NEXT: stvx v4, 0, r3 +; CHECK-P8-NEXT: lbz r4, 47(r1) +; CHECK-P8-NEXT: xori r4, r4, 128 +; CHECK-P8-NEXT: stb r4, 47(r1) +; CHECK-P8-NEXT: lvx v4, 0, r3 ; CHECK-P8-NEXT: bl fmaf128 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: xor r4, r4, r30 -; CHECK-P8-NEXT: addi r1, r1, 48 +; CHECK-P8-NEXT: addi r3, r1, 48 +; CHECK-P8-NEXT: stvx v2, 0, r3 +; CHECK-P8-NEXT: lbz r4, 63(r1) +; CHECK-P8-NEXT: xori r4, r4, 128 +; CHECK-P8-NEXT: stb r4, 63(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr %neg = fneg fp128 %f2 diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll index ad32202ba905..438e1768beab 100644 --- a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll +++ b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ -; RUN: < %s -enable-soft-fp128 -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s \ +; RUN: < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s \ ; RUN: -check-prefix=P8 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 \ diff --git a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll index 6f4b4a41c604..6749d5f948df 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ @@ -8,642 +9,598 @@ ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt define i64 @setb1(i64 %a, i64 %b) { +; CHECK-LABEL: setb1: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb1: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r3, r4 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: addic r7, r6, -1 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: subfe r6, r7, r6 +; CHECK-PWR8-NEXT: isellt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i64 %a, %b %t2 = icmp ne i64 %a, %b %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb1: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: addic -; CHECK-NOT: subfe -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb1 -; CHECK-PWR8-DAG: xor -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: addic -; CHECK-PWR8-DAG: subfe -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt define i64 @setb2(i64 %a, i64 %b) { +; CHECK-LABEL: setb2: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb2: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r3, r4 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: addic r7, r6, -1 +; CHECK-PWR8-NEXT: cmpd r4, r3 +; CHECK-PWR8-NEXT: subfe r6, r7, r6 +; CHECK-PWR8-NEXT: iselgt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp sgt i64 %b, %a %t2 = icmp ne i64 %a, %b %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb2: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: addic -; CHECK-NOT: subfe -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb2 -; CHECK-PWR8-DAG: xor -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: addic -; CHECK-PWR8-DAG: subfe -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt define i64 @setb3(i64 %a, i64 %b) { +; CHECK-LABEL: setb3: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb3: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r4, r3 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: addic r7, r6, -1 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: subfe r6, r7, r6 +; CHECK-PWR8-NEXT: isellt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i64 %a, %b %t2 = icmp ne i64 %b, %a %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb3: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: addic -; CHECK-NOT: subfe -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb3 -; CHECK-PWR8-DAG: xor -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: addic -; CHECK-PWR8-DAG: subfe -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt define i64 @setb4(i64 %a, i64 %b) { +; CHECK-LABEL: setb4: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb4: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r4, r3 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: addic r7, r6, -1 +; CHECK-PWR8-NEXT: cmpd r4, r3 +; CHECK-PWR8-NEXT: subfe r6, r7, r6 +; CHECK-PWR8-NEXT: iselgt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp sgt i64 %b, %a %t2 = icmp ne i64 %b, %a %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb4: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: addic -; CHECK-NOT: subfe -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb4 -; CHECK-PWR8-DAG: xor -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: addic -; CHECK-PWR8-DAG: subfe -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt define i64 @setb5(i64 %a, i64 %b) { +; CHECK-LABEL: setb5: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb5: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: sradi r6, r4, 63 +; CHECK-PWR8-NEXT: rldicl r7, r3, 1, 63 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: subc r8, r4, r3 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: adde r6, r7, r6 +; CHECK-PWR8-NEXT: xori r6, r6, 1 +; CHECK-PWR8-NEXT: isellt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i64 %a, %b %t2 = icmp sgt i64 %a, %b %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb5: -; CHECK-NOT: sradi -; CHECK-NOT: rldicl -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subc -; CHECK-NOT: adde -; CHECK-NOT: xori -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb5 -; CHECK-PWR8-DAG: sradi -; CHECK-PWR8-DAG: rldicl -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: subc -; CHECK-PWR8-DAG: adde -; CHECK-PWR8-DAG: xori -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt define i64 @setb6(i64 %a, i64 %b) { +; CHECK-LABEL: setb6: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb6: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: sradi r6, r4, 63 +; CHECK-PWR8-NEXT: rldicl r7, r3, 1, 63 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: subc r8, r4, r3 +; CHECK-PWR8-NEXT: cmpd r4, r3 +; CHECK-PWR8-NEXT: adde r6, r7, r6 +; CHECK-PWR8-NEXT: xori r6, r6, 1 +; CHECK-PWR8-NEXT: iselgt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp sgt i64 %b, %a %t2 = icmp sgt i64 %a, %b %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb6: -; CHECK-NOT: sradi -; CHECK-NOT: rldicl -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subc -; CHECK-NOT: adde -; CHECK-NOT: xori -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb6 -; CHECK-PWR8-DAG: sradi -; CHECK-PWR8-DAG: rldicl -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: subc -; CHECK-PWR8-DAG: adde -; CHECK-PWR8-DAG: xori -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt define i64 @setb7(i64 %a, i64 %b) { +; CHECK-LABEL: setb7: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb7: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: sradi r6, r4, 63 +; CHECK-PWR8-NEXT: rldicl r7, r3, 1, 63 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: subc r8, r4, r3 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: adde r6, r7, r6 +; CHECK-PWR8-NEXT: xori r6, r6, 1 +; CHECK-PWR8-NEXT: isellt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i64 %a, %b %t2 = icmp slt i64 %b, %a %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb7: -; CHECK-NOT: sradi -; CHECK-NOT: rldicl -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subc -; CHECK-NOT: adde -; CHECK-NOT: xori -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb7 -; CHECK-PWR8-DAG: sradi -; CHECK-PWR8-DAG: rldicl -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: subc -; CHECK-PWR8-DAG: adde -; CHECK-PWR8-DAG: xori -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt define i64 @setb8(i64 %a, i64 %b) { +; CHECK-LABEL: setb8: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb8: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: sradi r6, r4, 63 +; CHECK-PWR8-NEXT: rldicl r7, r3, 1, 63 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: subc r8, r4, r3 +; CHECK-PWR8-NEXT: cmpd r4, r3 +; CHECK-PWR8-NEXT: adde r6, r7, r6 +; CHECK-PWR8-NEXT: xori r6, r6, 1 +; CHECK-PWR8-NEXT: iselgt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp sgt i64 %b, %a %t2 = icmp slt i64 %b, %a %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb8: -; CHECK-NOT: sradi -; CHECK-NOT: rldicl -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subc -; CHECK-NOT: adde -; CHECK-NOT: xori -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb8 -; CHECK-PWR8-DAG: sradi -; CHECK-PWR8-DAG: rldicl -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: subc -; CHECK-PWR8-DAG: adde -; CHECK-PWR8-DAG: xori -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setgt define i64 @setb9(i64 %a, i64 %b) { +; CHECK-LABEL: setb9: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb9: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r3, r4 +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: subfic r6, r6, 0 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: subfe r3, r6, r6 +; CHECK-PWR8-NEXT: iselgt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp sgt i64 %a, %b %t2 = icmp ne i64 %a, %b %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb9: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subfic -; CHECK-NOT: subfe -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb9 -; CHECK-PWR8-DAG: xor -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: subfic -; CHECK-PWR8-DAG: subfe -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setlt define i64 @setb10(i64 %a, i64 %b) { +; CHECK-LABEL: setb10: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb10: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r3, r4 +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: subfic r6, r6, 0 +; CHECK-PWR8-NEXT: cmpd r4, r3 +; CHECK-PWR8-NEXT: subfe r3, r6, r6 +; CHECK-PWR8-NEXT: isellt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i64 %b, %a %t2 = icmp ne i64 %a, %b %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb10: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subfic -; CHECK-NOT: subfe -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb10 -; CHECK-PWR8-DAG: xor -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: subfic -; CHECK-PWR8-DAG: subfe -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setgt define i64 @setb11(i64 %a, i64 %b) { +; CHECK-LABEL: setb11: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb11: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r4, r3 +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: subfic r6, r6, 0 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: subfe r3, r6, r6 +; CHECK-PWR8-NEXT: iselgt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp sgt i64 %a, %b %t2 = icmp ne i64 %b, %a %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb11: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subfic -; CHECK-NOT: subfe -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb11 -; CHECK-PWR8-DAG: xor -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: subfic -; CHECK-PWR8-DAG: subfe -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setlt define i64 @setb12(i64 %a, i64 %b) { +; CHECK-LABEL: setb12: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb12: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r4, r3 +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: subfic r6, r6, 0 +; CHECK-PWR8-NEXT: cmpd r4, r3 +; CHECK-PWR8-NEXT: subfe r3, r6, r6 +; CHECK-PWR8-NEXT: isellt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i64 %b, %a %t2 = icmp ne i64 %b, %a %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb12: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subfic -; CHECK-NOT: subfe -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb12 -; CHECK-PWR8-DAG: xor -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: subfic -; CHECK-PWR8-DAG: subfe -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setlt)), setgt define i64 @setb13(i64 %a, i64 %b) { +; CHECK-LABEL: setb13: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb13: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: sradi r6, r3, 63 +; CHECK-PWR8-NEXT: rldicl r7, r4, 1, 63 +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: subc r8, r3, r4 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: adde r6, r7, r6 +; CHECK-PWR8-NEXT: xori r6, r6, 1 +; CHECK-PWR8-NEXT: neg r6, r6 +; CHECK-PWR8-NEXT: iselgt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp sgt i64 %a, %b %t2 = icmp slt i64 %a, %b %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb13: -; CHECK-NOT: sradi -; CHECK-NOT: rldicl -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subc -; CHECK-NOT: adde -; CHECK-NOT: xori -; CHECK-NOT: neg -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb13 -; CHECK-PWR8-DAG: sradi -; CHECK-PWR8-DAG: rldicl -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: subc -; CHECK-PWR8-DAG: adde -; CHECK-PWR8-DAG: xori -; CHECK-PWR8-DAG: neg -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setlt)), setlt define i64 @setb14(i64 %a, i64 %b) { +; CHECK-LABEL: setb14: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb14: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: sradi r6, r3, 63 +; CHECK-PWR8-NEXT: rldicl r7, r4, 1, 63 +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: subc r8, r3, r4 +; CHECK-PWR8-NEXT: cmpd r4, r3 +; CHECK-PWR8-NEXT: adde r6, r7, r6 +; CHECK-PWR8-NEXT: xori r6, r6, 1 +; CHECK-PWR8-NEXT: neg r6, r6 +; CHECK-PWR8-NEXT: isellt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i64 %b, %a %t2 = icmp slt i64 %a, %b %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb14: -; CHECK-NOT: sradi -; CHECK-NOT: rldicl -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subc -; CHECK-NOT: adde -; CHECK-NOT: xori -; CHECK-NOT: neg -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb14 -; CHECK-PWR8-DAG: sradi -; CHECK-PWR8-DAG: rldicl -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: subc -; CHECK-PWR8-DAG: adde -; CHECK-PWR8-DAG: xori -; CHECK-PWR8-DAG: neg -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setgt)), setgt define i64 @setb15(i64 %a, i64 %b) { +; CHECK-LABEL: setb15: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb15: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: sradi r6, r3, 63 +; CHECK-PWR8-NEXT: rldicl r7, r4, 1, 63 +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: subc r8, r3, r4 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: adde r6, r7, r6 +; CHECK-PWR8-NEXT: xori r6, r6, 1 +; CHECK-PWR8-NEXT: neg r6, r6 +; CHECK-PWR8-NEXT: iselgt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp sgt i64 %a, %b %t2 = icmp sgt i64 %b, %a %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb15: -; CHECK-NOT: sradi -; CHECK-NOT: rldicl -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subc -; CHECK-NOT: adde -; CHECK-NOT: xori -; CHECK-NOT: neg -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb15 -; CHECK-PWR8-DAG: sradi -; CHECK-PWR8-DAG: rldicl -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: subc -; CHECK-PWR8-DAG: adde -; CHECK-PWR8-DAG: xori -; CHECK-PWR8-DAG: neg -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt define i64 @setb16(i64 %a, i64 %b) { +; CHECK-LABEL: setb16: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb16: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: sradi r6, r3, 63 +; CHECK-PWR8-NEXT: rldicl r7, r4, 1, 63 +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: subc r8, r3, r4 +; CHECK-PWR8-NEXT: cmpd r4, r3 +; CHECK-PWR8-NEXT: adde r6, r7, r6 +; CHECK-PWR8-NEXT: xori r6, r6, 1 +; CHECK-PWR8-NEXT: neg r6, r6 +; CHECK-PWR8-NEXT: isellt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i64 %b, %a %t2 = icmp sgt i64 %b, %a %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb16: -; CHECK-NOT: sradi -; CHECK-NOT: rldicl -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subc -; CHECK-NOT: adde -; CHECK-NOT: xori -; CHECK-NOT: neg -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb16 -; CHECK-PWR8-DAG: sradi -; CHECK-PWR8-DAG: rldicl -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: subc -; CHECK-PWR8-DAG: adde -; CHECK-PWR8-DAG: xori -; CHECK-PWR8-DAG: neg -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, 1, -1, setgt), seteq define i64 @setb17(i64 %a, i64 %b) { +; CHECK-LABEL: setb17: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb17: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: li r6, 1 +; CHECK-PWR8-NEXT: iselgt r5, r6, r5 +; CHECK-PWR8-NEXT: cmpld r3, r4 +; CHECK-PWR8-NEXT: iseleq r3, 0, r5 +; CHECK-PWR8-NEXT: blr %t1 = icmp eq i64 %a, %b %t2 = icmp sgt i64 %a, %b %t3 = select i1 %t2, i64 1, i64 -1 %t4 = select i1 %t1, i64 0, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb17: -; CHECK-NOT: li -; CHECK-NOT: cmpld -; CHECK-NOT: isel -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb17 -; CHECK-PWR8: cmpd -; CHECK-PWR8: isel -; CHECK-PWR8: cmpld -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, 1, -1, setgt), seteq define i64 @setb18(i64 %a, i64 %b) { +; CHECK-LABEL: setb18: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb18: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: li r6, 1 +; CHECK-PWR8-NEXT: iselgt r5, r6, r5 +; CHECK-PWR8-NEXT: cmpld r4, r3 +; CHECK-PWR8-NEXT: iseleq r3, 0, r5 +; CHECK-PWR8-NEXT: blr %t1 = icmp eq i64 %b, %a %t2 = icmp sgt i64 %a, %b %t3 = select i1 %t2, i64 1, i64 -1 %t4 = select i1 %t1, i64 0, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb18: -; CHECK-NOT: li -; CHECK-NOT: cmpld -; CHECK-NOT: isel -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb18 -; CHECK-PWR8: cmpd -; CHECK-PWR8: isel -; CHECK-PWR8: cmpld -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, 1, -1, setlt), seteq define i64 @setb19(i64 %a, i64 %b) { +; CHECK-LABEL: setb19: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb19: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: cmpd r4, r3 +; CHECK-PWR8-NEXT: li r6, 1 +; CHECK-PWR8-NEXT: isellt r5, r6, r5 +; CHECK-PWR8-NEXT: cmpld r3, r4 +; CHECK-PWR8-NEXT: iseleq r3, 0, r5 +; CHECK-PWR8-NEXT: blr %t1 = icmp eq i64 %a, %b %t2 = icmp slt i64 %b, %a %t3 = select i1 %t2, i64 1, i64 -1 %t4 = select i1 %t1, i64 0, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb19: -; CHECK-NOT: li -; CHECK-NOT: cmpld -; CHECK-NOT: isel -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb19 -; CHECK-PWR8: cmpd -; CHECK-PWR8: isel -; CHECK-PWR8: cmpld -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, 1, -1, setlt), seteq define i64 @setb20(i64 %a, i64 %b) { +; CHECK-LABEL: setb20: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb20: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: cmpd r4, r3 +; CHECK-PWR8-NEXT: li r6, 1 +; CHECK-PWR8-NEXT: isellt r5, r6, r5 +; CHECK-PWR8-NEXT: cmpld r4, r3 +; CHECK-PWR8-NEXT: iseleq r3, 0, r5 +; CHECK-PWR8-NEXT: blr %t1 = icmp eq i64 %b, %a %t2 = icmp slt i64 %b, %a %t3 = select i1 %t2, i64 1, i64 -1 %t4 = select i1 %t1, i64 0, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb20: -; CHECK-NOT: li -; CHECK-NOT: cmpld -; CHECK-NOT: isel -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb20 -; CHECK-PWR8: cmpd -; CHECK-PWR8: isel -; CHECK-PWR8: cmpld -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setlt), seteq define i64 @setb21(i64 %a, i64 %b) { +; CHECK-LABEL: setb21: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb21: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: li r6, -1 +; CHECK-PWR8-NEXT: isellt r5, r6, r5 +; CHECK-PWR8-NEXT: cmpld r3, r4 +; CHECK-PWR8-NEXT: iseleq r3, 0, r5 +; CHECK-PWR8-NEXT: blr %t1 = icmp eq i64 %a, %b %t2 = icmp slt i64 %a, %b %t3 = select i1 %t2, i64 -1, i64 1 %t4 = select i1 %t1, i64 0, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb21: -; CHECK-NOT: li -; CHECK-NOT: cmpld -; CHECK-NOT: isel -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb21 -; CHECK-PWR8: cmpd -; CHECK-PWR8: isel -; CHECK-PWR8: cmpld -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setlt), seteq define i64 @setb22(i64 %a, i64 %b) { +; CHECK-LABEL: setb22: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb22: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: li r6, -1 +; CHECK-PWR8-NEXT: isellt r5, r6, r5 +; CHECK-PWR8-NEXT: cmpld r4, r3 +; CHECK-PWR8-NEXT: iseleq r3, 0, r5 +; CHECK-PWR8-NEXT: blr %t1 = icmp eq i64 %b, %a %t2 = icmp slt i64 %a, %b %t3 = select i1 %t2, i64 -1, i64 1 %t4 = select i1 %t1, i64 0, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb22: -; CHECK-NOT: li -; CHECK-NOT: cmpld -; CHECK-NOT: isel -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb22 -; CHECK-PWR8: cmpd -; CHECK-PWR8: isel -; CHECK-PWR8: cmpld -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setgt), seteq define i64 @setb23(i64 %a, i64 %b) { +; CHECK-LABEL: setb23: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb23: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: cmpd r4, r3 +; CHECK-PWR8-NEXT: li r6, -1 +; CHECK-PWR8-NEXT: iselgt r5, r6, r5 +; CHECK-PWR8-NEXT: cmpld r3, r4 +; CHECK-PWR8-NEXT: iseleq r3, 0, r5 +; CHECK-PWR8-NEXT: blr %t1 = icmp eq i64 %a, %b %t2 = icmp sgt i64 %b, %a %t3 = select i1 %t2, i64 -1, i64 1 %t4 = select i1 %t1, i64 0, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb23: -; CHECK-NOT: li -; CHECK-NOT: cmpld -; CHECK-NOT: isel -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb23 -; CHECK-PWR8: cmpd -; CHECK-PWR8: isel -; CHECK-PWR8: cmpld -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setgt), seteq define i64 @setb24(i64 %a, i64 %b) { +; CHECK-LABEL: setb24: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb24: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: cmpd r4, r3 +; CHECK-PWR8-NEXT: li r6, -1 +; CHECK-PWR8-NEXT: iselgt r5, r6, r5 +; CHECK-PWR8-NEXT: cmpld r4, r3 +; CHECK-PWR8-NEXT: iseleq r3, 0, r5 +; CHECK-PWR8-NEXT: blr %t1 = icmp eq i64 %b, %a %t2 = icmp sgt i64 %b, %a %t3 = select i1 %t2, i64 -1, i64 1 %t4 = select i1 %t1, i64 0, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb24: -; CHECK-NOT: li -; CHECK-NOT: cmpld -; CHECK-NOT: isel -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb24 -; CHECK-PWR8: cmpd -; CHECK-PWR8: isel -; CHECK-PWR8: cmpld -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; end all patterns testing for i64 @@ -651,51 +608,50 @@ define i64 @setb24(i64 %a, i64 %b) { ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt define i64 @setb25(i64 %a, i64 %b) { +; CHECK-LABEL: setb25: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r4, r3 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb25: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r4, r3 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: addic r7, r6, -1 +; CHECK-PWR8-NEXT: cmpd r4, r3 +; CHECK-PWR8-NEXT: subfe r6, r7, r6 +; CHECK-PWR8-NEXT: isellt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i64 %b, %a %t2 = icmp ne i64 %b, %a %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb25: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK-NOT: cmpd -; CHECK: cmpd {{c?r?(0, )?}}r4, r3 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: addic -; CHECK-NOT: subfe -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb25 -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: addic -; CHECK-PWR8-DAG: subfe -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt define i64 @setb26(i64 %a, i64 %b) { +; CHECK-LABEL: setb26: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r4, r3 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb26: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r4, r3 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: addic r7, r6, -1 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: subfe r6, r7, r6 +; CHECK-PWR8-NEXT: iselgt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp sgt i64 %a, %b %t2 = icmp ne i64 %b, %a %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setb26: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r4, r3 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: addic -; CHECK-NOT: subfe -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb26 -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: addic -; CHECK-PWR8-DAG: subfe -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; Test with different scalar integer type for selected value @@ -703,83 +659,85 @@ define i64 @setb26(i64 %a, i64 %b) { ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt define i64 @setb27(i64 %a, i64 %b) { +; CHECK-LABEL: setb27: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: extsw r3, r3 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb27: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r4, r3 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: addic r7, r6, -1 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: subfe r6, r7, r6 +; CHECK-PWR8-NEXT: isellt r3, r5, r6 +; CHECK-PWR8-NEXT: extsw r3, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i64 %a, %b %t2 = icmp ne i64 %b, %a %t3 = zext i1 %t2 to i32 %t4 = select i1 %t1, i32 -1, i32 %t3 %t5 = sext i32 %t4 to i64 ret i64 %t5 -; CHECK-LABEL: setb27: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: addic -; CHECK-NOT: subfe -; CHECK-NOT: isel -; CHECK: extsw -; CHECK: blr -; CHECK-PWR8-LABEL: setb27 -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: addic -; CHECK-PWR8-DAG: subfe -; CHECK-PWR8: isel -; CHECK-PWR8: extsw -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt define i64 @setb28(i64 %a, i64 %b) { +; CHECK-LABEL: setb28: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: extsw r3, r3 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb28: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r4, r3 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: addic r7, r6, -1 +; CHECK-PWR8-NEXT: cmpd r4, r3 +; CHECK-PWR8-NEXT: subfe r6, r7, r6 +; CHECK-PWR8-NEXT: iselgt r3, r5, r6 +; CHECK-PWR8-NEXT: extsw r3, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp sgt i64 %b, %a %t2 = icmp ne i64 %b, %a %t3 = zext i1 %t2 to i16 %t4 = select i1 %t1, i16 -1, i16 %t3 %t5 = sext i16 %t4 to i64 ret i64 %t5 -; CHECK-LABEL: setb28: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: addic -; CHECK-NOT: subfe -; CHECK-NOT: isel -; CHECK: extsw -; CHECK: blr -; CHECK-PWR8-LABEL: setb28 -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: addic -; CHECK-PWR8-DAG: subfe -; CHECK-PWR8: isel -; CHECK-PWR8: extsw -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt define i64 @setb29(i64 %a, i64 %b) { +; CHECK-LABEL: setb29: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: clrldi r3, r3, 56 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setb29: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: sradi r6, r4, 63 +; CHECK-PWR8-NEXT: rldicl r7, r3, 1, 63 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: subc r8, r4, r3 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: adde r6, r7, r6 +; CHECK-PWR8-NEXT: xori r6, r6, 1 +; CHECK-PWR8-NEXT: isellt r3, r5, r6 +; CHECK-PWR8-NEXT: clrldi r3, r3, 56 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i64 %a, %b %t2 = icmp sgt i64 %a, %b %t3 = zext i1 %t2 to i8 %t4 = select i1 %t1, i8 -1, i8 %t3 %t5 = zext i8 %t4 to i64 ret i64 %t5 -; CHECK-LABEL: setb29: -; CHECK-NOT: sradi -; CHECK-NOT: rldicl -; CHECK-NOT: li -; CHECK: cmpd {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subc -; CHECK-NOT: adde -; CHECK-NOT: xori -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setb29 -; CHECK-PWR8-DAG: cmpd -; CHECK-PWR8-DAG: subc -; CHECK-PWR8-DAG: adde -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; Testings to cover different comparison opcodes @@ -787,555 +745,673 @@ define i64 @setb29(i64 %a, i64 %b) { ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt define i64 @setbsw1(i32 %a, i32 %b) { +; CHECK-LABEL: setbsw1: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpw r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbsw1: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r3, r4 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: cntlzw r6, r6 +; CHECK-PWR8-NEXT: cmpw r3, r4 +; CHECK-PWR8-NEXT: srwi r6, r6, 5 +; CHECK-PWR8-NEXT: xori r3, r6, 1 +; CHECK-PWR8-NEXT: isellt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i32 %a, %b %t2 = icmp ne i32 %a, %b %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbsw1: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpw {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: cntlzw -; CHECK-NOT: srwi -; CHECK-NOT: xori -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbsw1 -; CHECK-PWR8-DAG: cntlzw -; CHECK-PWR8-DAG: cmpw -; CHECK-PWR8-DAG: srwi -; CHECK-PWR8-DAG: xori -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt define i64 @setbsw2(i32 %a, i32 %b) { +; CHECK-LABEL: setbsw2: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpw r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbsw2: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r3, r4 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: cntlzw r6, r6 +; CHECK-PWR8-NEXT: cmpw r4, r3 +; CHECK-PWR8-NEXT: srwi r6, r6, 5 +; CHECK-PWR8-NEXT: xori r3, r6, 1 +; CHECK-PWR8-NEXT: iselgt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp sgt i32 %b, %a %t2 = icmp ne i32 %a, %b %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbsw2: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpw {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: cntlzw -; CHECK-NOT: srwi -; CHECK-NOT: xori -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbsw2 -; CHECK-PWR8-DAG: cntlzw -; CHECK-PWR8-DAG: cmpw -; CHECK-PWR8-DAG: srwi -; CHECK-PWR8-DAG: xori -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setgt), seteq define i64 @setbsw3(i32 %a, i32 %b) { +; CHECK-LABEL: setbsw3: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpw r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbsw3: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: cmpw r4, r3 +; CHECK-PWR8-NEXT: li r6, -1 +; CHECK-PWR8-NEXT: iselgt r5, r6, r5 +; CHECK-PWR8-NEXT: cmplw r3, r4 +; CHECK-PWR8-NEXT: iseleq r3, 0, r5 +; CHECK-PWR8-NEXT: blr %t1 = icmp eq i32 %a, %b %t2 = icmp sgt i32 %b, %a %t3 = select i1 %t2, i64 -1, i64 1 %t4 = select i1 %t1, i64 0, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbsw3: -; CHECK-NOT: li -; CHECK: cmpw {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: isel -; CHECK-NOT: cmplw -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbsw3 -; CHECK-PWR8: cmpw -; CHECK-PWR8: isel -; CHECK-PWR8: cmplw -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt define i64 @setbsh1(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: setbsh1: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpw r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbsh1: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r4, r3 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: cntlzw r6, r6 +; CHECK-PWR8-NEXT: cmpw r3, r4 +; CHECK-PWR8-NEXT: srwi r6, r6, 5 +; CHECK-PWR8-NEXT: xori r3, r6, 1 +; CHECK-PWR8-NEXT: isellt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i16 %a, %b %t2 = icmp ne i16 %b, %a %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbsh1: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpw {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: cntlzw -; CHECK-NOT: srwi -; CHECK-NOT: xori -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbsh1 -; CHECK-PWR8-DAG: cntlzw -; CHECK-PWR8-DAG: cmpw -; CHECK-PWR8-DAG: srwi -; CHECK-PWR8-DAG: xori -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt define i64 @setbsh2(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: setbsh2: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpw r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbsh2: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r4, r3 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: cntlzw r6, r6 +; CHECK-PWR8-NEXT: cmpw r4, r3 +; CHECK-PWR8-NEXT: srwi r6, r6, 5 +; CHECK-PWR8-NEXT: xori r3, r6, 1 +; CHECK-PWR8-NEXT: iselgt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp sgt i16 %b, %a %t2 = icmp ne i16 %b, %a %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbsh2: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpw {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: cntlzw -; CHECK-NOT: srwi -; CHECK-NOT: xori -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbsh2 -; CHECK-PWR8-DAG: cmpw -; CHECK-PWR8-DAG: cntlzw -; CHECK-PWR8-DAG: srwi -; CHECK-PWR8-DAG: xori -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt define i64 @setbsc1(i8 %a, i8 %b) { +; CHECK-LABEL: setbsc1: +; CHECK: # %bb.0: +; CHECK-NEXT: extsb r4, r4 +; CHECK-NEXT: extsb r3, r3 +; CHECK-NEXT: cmpw r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbsc1: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: extsb r4, r4 +; CHECK-PWR8-NEXT: extsb r3, r3 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: extsw r4, r4 +; CHECK-PWR8-NEXT: extsw r3, r3 +; CHECK-PWR8-NEXT: sub r6, r4, r3 +; CHECK-PWR8-NEXT: cmpw r3, r4 +; CHECK-PWR8-NEXT: rldicl r3, r6, 1, 63 +; CHECK-PWR8-NEXT: isellt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i8 %a, %b %t2 = icmp sgt i8 %a, %b %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbsc1: -; CHECK-DAG: extsb [[RA:r[0-9]+]], r3 -; CHECK-DAG: extsb [[RB:r[0-9]+]], r4 -; CHECK-NOT: li -; CHECK-NOT: sub -; CHECK: cmpw {{c?r?(0, )?}}[[RA]], [[RB]] -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: rldicl -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbsc1 -; CHECK-PWR8-DAG: extsb -; CHECK-PWR8-DAG: extsb -; CHECK-PWR8-DAG: extsw -; CHECK-PWR8-DAG: extsw -; CHECK-PWR8-DAG: cmpw -; CHECK-PWR8-DAG: rldicl -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt define i64 @setbsc2(i8 %a, i8 %b) { +; CHECK-LABEL: setbsc2: +; CHECK: # %bb.0: +; CHECK-NEXT: extsb r4, r4 +; CHECK-NEXT: extsb r3, r3 +; CHECK-NEXT: cmpw r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbsc2: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: extsb r4, r4 +; CHECK-PWR8-NEXT: extsb r3, r3 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: extsw r4, r4 +; CHECK-PWR8-NEXT: extsw r3, r3 +; CHECK-PWR8-NEXT: sub r6, r4, r3 +; CHECK-PWR8-NEXT: cmpw r4, r3 +; CHECK-PWR8-NEXT: rldicl r3, r6, 1, 63 +; CHECK-PWR8-NEXT: iselgt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp sgt i8 %b, %a %t2 = icmp sgt i8 %a, %b %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbsc2: -; CHECK-DAG: extsb [[RA:r[0-9]+]], r3 -; CHECK-DAG: extsb [[RB:r[0-9]+]], r4 -; CHECK-NOT: li -; CHECK-NOT: sub -; CHECK: cmpw {{c?r?(0, )?}}[[RA]], [[RB]] -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: rldicl -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbsc2 -; CHECK-PWR8-DAG: extsb -; CHECK-PWR8-DAG: extsb -; CHECK-PWR8-DAG: extsw -; CHECK-PWR8-DAG: extsw -; CHECK-PWR8-DAG: cmpw -; CHECK-PWR8-DAG: rldicl -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt define i64 @setbsc3(i4 %a, i4 %b) { +; CHECK-LABEL: setbsc3: +; CHECK: # %bb.0: +; CHECK-NEXT: slwi r4, r4, 28 +; CHECK-NEXT: slwi r3, r3, 28 +; CHECK-NEXT: srawi r4, r4, 28 +; CHECK-NEXT: srawi r3, r3, 28 +; CHECK-NEXT: cmpw r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbsc3: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: slwi r4, r4, 28 +; CHECK-PWR8-NEXT: slwi r3, r3, 28 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: srawi r4, r4, 28 +; CHECK-PWR8-NEXT: srawi r3, r3, 28 +; CHECK-PWR8-NEXT: extsw r4, r4 +; CHECK-PWR8-NEXT: extsw r3, r3 +; CHECK-PWR8-NEXT: sub r6, r4, r3 +; CHECK-PWR8-NEXT: cmpw r3, r4 +; CHECK-PWR8-NEXT: rldicl r3, r6, 1, 63 +; CHECK-PWR8-NEXT: isellt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i4 %a, %b %t2 = icmp slt i4 %b, %a %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbsc3: -; CHECK-DAG: slwi [[RA:r[0-9]+]], r3, 28 -; CHECK-DAG: slwi [[RB:r[0-9]+]], r4, 28 -; CHECK-NOT: li -; CHECK-DAG: srawi [[RA1:r[0-9]+]], [[RA]], 28 -; CHECK-DAG: srawi [[RB1:r[0-9]+]], [[RB]], 28 -; CHECK-NOT: sub -; CHECK: cmpw {{c?r?(0, )?}}[[RA1]], [[RB1]] -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: rldicl -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbsc3 -; CHECK-PWR8-DAG: slwi -; CHECK-PWR8-DAG: slwi -; CHECK-PWR8-DAG: srawi -; CHECK-PWR8-DAG: srawi -; CHECK-PWR8-DAG: extsw -; CHECK-PWR8-DAG: extsw -; CHECK-PWR8-DAG: cmpw -; CHECK-PWR8-DAG: rldicl -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; Test with unsigned integer type i64/i32/i16/i8 for input parameter ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setult)), setugt define i64 @setbud1(i64 %a, i64 %b) { +; CHECK-LABEL: setbud1: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpld r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbud1: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: subc r6, r4, r3 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: subfe r6, r4, r4 +; CHECK-PWR8-NEXT: cmpld r4, r3 +; CHECK-PWR8-NEXT: neg r3, r6 +; CHECK-PWR8-NEXT: iselgt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp ugt i64 %b, %a %t2 = icmp ult i64 %b, %a %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbud1: -; CHECK-NOT: li -; CHECK: cmpld {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subc -; CHECK-NOT: subfe -; CHECK-NOT: neg -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbud1 -; CHECK-PWR8-DAG: subc -; CHECK-PWR8-DAG: subfe -; CHECK-PWR8-DAG: cmpld -; CHECK-PWR8-DAG: neg -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setugt define i64 @setbud2(i64 %a, i64 %b) { +; CHECK-LABEL: setbud2: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpld r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbud2: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r3, r4 +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: subfic r6, r6, 0 +; CHECK-PWR8-NEXT: cmpld r3, r4 +; CHECK-PWR8-NEXT: subfe r3, r6, r6 +; CHECK-PWR8-NEXT: iselgt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp ugt i64 %a, %b %t2 = icmp ne i64 %a, %b %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbud2: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmpld {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: subfic -; CHECK-NOT: subfe -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbud2 -; CHECK-PWR8-DAG: cmpld -; CHECK-PWR8-DAG: subfic -; CHECK-PWR8-DAG: subfe -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setugt), seteq define i64 @setbud3(i64 %a, i64 %b) { +; CHECK-LABEL: setbud3: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpld r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbud3: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: cmpld r4, r3 +; CHECK-PWR8-NEXT: li r3, -1 +; CHECK-PWR8-NEXT: iselgt r3, r3, r5 +; CHECK-PWR8-NEXT: iseleq r3, 0, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp eq i64 %b, %a %t2 = icmp ugt i64 %b, %a %t3 = select i1 %t2, i64 -1, i64 1 %t4 = select i1 %t1, i64 0, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbud3: -; CHECK-NOT: li -; CHECK: cmpld {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: li -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbud3 -; CHECK-PWR8-DAG: cmpld -; CHECK-PWR8-DAG: li -; CHECK-PWR8-DAG: li -; CHECK-PWR8: isel -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setult define i64 @setbuw1(i32 %a, i32 %b) { +; CHECK-LABEL: setbuw1: +; CHECK: # %bb.0: +; CHECK-NEXT: cmplw r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbuw1: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r3, r4 +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: cntlzw r6, r6 +; CHECK-PWR8-NEXT: cmplw r4, r3 +; CHECK-PWR8-NEXT: srwi r6, r6, 5 +; CHECK-PWR8-NEXT: xori r6, r6, 1 +; CHECK-PWR8-NEXT: neg r3, r6 +; CHECK-PWR8-NEXT: isellt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp ult i32 %b, %a %t2 = icmp ne i32 %a, %b %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbuw1: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmplw {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: cntlzw -; CHECK-NOT: srwi -; CHECK-NOT: xori -; CHECK-NOT: neg -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbuw1 -; CHECK-PWR8-DAG: cntlzw -; CHECK-PWR8-DAG: cmplw -; CHECK-PWR8-DAG: srwi -; CHECK-PWR8-DAG: xori -; CHECK-PWR8-DAG: neg -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setugt define i64 @setbuw2(i32 %a, i32 %b) { +; CHECK-LABEL: setbuw2: +; CHECK: # %bb.0: +; CHECK-NEXT: cmplw r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbuw2: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r4, r3 +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: cntlzw r6, r6 +; CHECK-PWR8-NEXT: cmplw r3, r4 +; CHECK-PWR8-NEXT: srwi r6, r6, 5 +; CHECK-PWR8-NEXT: xori r6, r6, 1 +; CHECK-PWR8-NEXT: neg r3, r6 +; CHECK-PWR8-NEXT: iselgt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp ugt i32 %a, %b %t2 = icmp ne i32 %b, %a %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbuw2: -; CHECK-NOT: xor -; CHECK-NOT: li -; CHECK: cmplw {{c?r?(0, )?}}r3, r4 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: cntlzw -; CHECK-NOT: srwi -; CHECK-NOT: xori -; CHECK-NOT: neg -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbuw2 -; CHECK-PWR8-DAG: cntlzw -; CHECK-PWR8-DAG: cmplw -; CHECK-PWR8-DAG: srwi -; CHECK-PWR8-DAG: xori -; CHECK-PWR8-DAG: neg -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setult define i64 @setbuh(i16 %a, i16 %b) { +; CHECK-LABEL: setbuh: +; CHECK: # %bb.0: +; CHECK-NEXT: clrlwi r4, r4, 16 +; CHECK-NEXT: clrlwi r3, r3, 16 +; CHECK-NEXT: cmplw r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbuh: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: clrlwi r3, r3, 16 +; CHECK-PWR8-NEXT: clrlwi r4, r4, 16 +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: xor r6, r4, r3 +; CHECK-PWR8-NEXT: cmplw r4, r3 +; CHECK-PWR8-NEXT: cntlzw r6, r6 +; CHECK-PWR8-NEXT: srwi r6, r6, 5 +; CHECK-PWR8-NEXT: xori r6, r6, 1 +; CHECK-PWR8-NEXT: neg r3, r6 +; CHECK-PWR8-NEXT: isellt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp ult i16 %b, %a %t2 = icmp ne i16 %b, %a %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbuh: -; CHECK-DAG: clrlwi [[RA:r[0-9]+]], r3, 16 -; CHECK-DAG: clrlwi [[RB:r[0-9]+]], r4, 16 -; CHECK-NOT: li -; CHECK-NOT: xor -; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]] -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: cntlzw -; CHECK-NOT: srwi -; CHECK-NOT: xori -; CHECK-NOT: neg -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbuh -; CHECK-PWR8: clrlwi -; CHECK-PWR8: clrlwi -; CHECK-PWR8-DAG: cmplw -; CHECK-PWR8-DAG: cntlzw -; CHECK-PWR8: srwi -; CHECK-PWR8: xori -; CHECK-PWR8: neg -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setult)), setugt define i64 @setbuc(i8 %a, i8 %b) { +; CHECK-LABEL: setbuc: +; CHECK: # %bb.0: +; CHECK-NEXT: clrlwi r4, r4, 24 +; CHECK-NEXT: clrlwi r3, r3, 24 +; CHECK-NEXT: cmplw r3, r4 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbuc: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: clrlwi r3, r3, 24 +; CHECK-PWR8-NEXT: clrlwi r4, r4, 24 +; CHECK-PWR8-NEXT: li r5, 1 +; CHECK-PWR8-NEXT: clrldi r6, r3, 32 +; CHECK-PWR8-NEXT: clrldi r7, r4, 32 +; CHECK-PWR8-NEXT: sub r6, r6, r7 +; CHECK-PWR8-NEXT: cmplw r3, r4 +; CHECK-PWR8-NEXT: sradi r6, r6, 63 +; CHECK-PWR8-NEXT: iselgt r3, r5, r6 +; CHECK-PWR8-NEXT: blr %t1 = icmp ugt i8 %a, %b %t2 = icmp ult i8 %a, %b %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbuc: -; CHECK-DAG: clrlwi [[RA:r[0-9]+]], r3, 24 -; CHECK-DAG: clrlwi [[RB:r[0-9]+]], r4, 24 -; CHECK-NOT: li -; CHECK-NOT: clrldi -; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]] -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: sub -; CHECK-NOT: sradi -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbuc -; CHECK-PWR8: clrlwi -; CHECK-PWR8: clrlwi -; CHECK-PWR8-DAG: clrldi -; CHECK-PWR8-DAG: clrldi -; CHECK-PWR8-DAG: cmplw -; CHECK-PWR8: sradi -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; Test with float/double/float128 for input parameter ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt define i64 @setbf1(float %a, float %b) { +; CHECK-LABEL: setbf1: +; CHECK: # %bb.0: +; CHECK-NEXT: fcmpu cr0, f1, f2 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbf1: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: fcmpu cr0, f2, f1 +; CHECK-PWR8-NEXT: fcmpu cr1, f1, f2 +; CHECK-PWR8-NEXT: li r3, 0 +; CHECK-PWR8-NEXT: li r4, 1 +; CHECK-PWR8-NEXT: isellt r3, r4, r3 +; CHECK-PWR8-NEXT: li r4, -1 +; CHECK-PWR8-NEXT: isel r3, r4, r3, 4*cr1+lt +; CHECK-PWR8-NEXT: blr %t1 = fcmp nnan olt float %a, %b %t2 = fcmp nnan olt float %b, %a %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbf1: -; CHECK-NOT: li -; CHECK: fcmpu cr0, f1, f2 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: isel -; CHECK-NOT: li -; CHECK: blr -; CHECK-PWR8-LABEL: setbf1 -; CHECK-PWR8: isel -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt define i64 @setbf2(float %a, float %b) { +; CHECK-LABEL: setbf2: +; CHECK: # %bb.0: +; CHECK-NEXT: fcmpu cr0, f1, f2 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbf2: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: fcmpu cr0, f2, f1 +; CHECK-PWR8-NEXT: li r3, 0 +; CHECK-PWR8-NEXT: li r4, 1 +; CHECK-PWR8-NEXT: isellt r3, r4, r3 +; CHECK-PWR8-NEXT: li r4, -1 +; CHECK-PWR8-NEXT: iselgt r3, r4, r3 +; CHECK-PWR8-NEXT: blr %t1 = fcmp nnan ogt float %b, %a %t2 = fcmp nnan olt float %b, %a %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbf2: -; CHECK-NOT: li -; CHECK: fcmpu cr0, f1, f2 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: isel -; CHECK-NOT: li -; CHECK: blr -; CHECK-PWR8-LABEL: setbf2 -; CHECK-PWR8: isel -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setgt), seteq define i64 @setbdf1(double %a, double %b) { +; CHECK-LABEL: setbdf1: +; CHECK: # %bb.0: +; CHECK-NEXT: xscmpudp cr0, f1, f2 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbdf1: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xscmpudp cr0, f2, f1 +; CHECK-PWR8-NEXT: li r3, 1 +; CHECK-PWR8-NEXT: li r4, -1 +; CHECK-PWR8-NEXT: iselgt r3, r4, r3 +; CHECK-PWR8-NEXT: iseleq r3, 0, r3 +; CHECK-PWR8-NEXT: blr %t1 = fcmp nnan oeq double %b, %a %t2 = fcmp nnan ogt double %b, %a %t3 = select i1 %t2, i64 -1, i64 1 %t4 = select i1 %t1, i64 0, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbdf1: -; CHECK: xscmpudp cr0, f1, f2 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: li -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbdf1 -; CHECK-PWR8: isel -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt define i64 @setbdf2(double %a, double %b) { +; CHECK-LABEL: setbdf2: +; CHECK: # %bb.0: +; CHECK-NEXT: xscmpudp cr0, f1, f2 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbdf2: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: fcmpu cr0, f2, f1 +; CHECK-PWR8-NEXT: xscmpudp cr1, f2, f1 +; CHECK-PWR8-NEXT: li r3, 0 +; CHECK-PWR8-NEXT: li r4, -1 +; CHECK-PWR8-NEXT: iselgt r3, r4, r3 +; CHECK-PWR8-NEXT: li r4, 1 +; CHECK-PWR8-NEXT: isel r3, r4, r3, 4*cr1+lt +; CHECK-PWR8-NEXT: blr %t1 = fcmp nnan olt double %b, %a %t2 = fcmp nnan ogt double %b, %a %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbdf2: -; CHECK-NOT: fcmpu -; CHECK-NOT: li -; CHECK: xscmpudp cr0, f1, f2 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: li -; CHECK-NOT: isel -; CHECK: blr -; CHECK-PWR8-LABEL: setbdf2 -; CHECK-PWR8: isel -; CHECK-PWR8: isel -; CHECK-PWR8: blr } define i64 @setbf128(fp128 %a, fp128 %b) { +; CHECK-LABEL: setbf128: +; CHECK: # %bb.0: +; CHECK-NEXT: xscmpuqp cr0, v2, v3 +; CHECK-NEXT: setb r3, cr0 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbf128: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: mflr r0 +; CHECK-PWR8-NEXT: std r0, 16(r1) +; CHECK-PWR8-NEXT: stdu r1, -96(r1) +; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 96 +; CHECK-PWR8-NEXT: .cfi_offset lr, 16 +; CHECK-PWR8-NEXT: .cfi_offset r30, -16 +; CHECK-PWR8-NEXT: .cfi_offset v30, -48 +; CHECK-PWR8-NEXT: .cfi_offset v31, -32 +; CHECK-PWR8-NEXT: li r3, 48 +; CHECK-PWR8-NEXT: std r30, 80(r1) # 8-byte Folded Spill +; CHECK-PWR8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill +; CHECK-PWR8-NEXT: li r3, 64 +; CHECK-PWR8-NEXT: vmr v30, v2 +; CHECK-PWR8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill +; CHECK-PWR8-NEXT: vmr v31, v3 +; CHECK-PWR8-NEXT: bl __ltkf2 +; CHECK-PWR8-NEXT: nop +; CHECK-PWR8-NEXT: vmr v2, v30 +; CHECK-PWR8-NEXT: srawi r30, r3, 31 +; CHECK-PWR8-NEXT: vmr v3, v31 +; CHECK-PWR8-NEXT: bl __gtkf2 +; CHECK-PWR8-NEXT: nop +; CHECK-PWR8-NEXT: li r4, 1 +; CHECK-PWR8-NEXT: cmpwi r3, 0 +; CHECK-PWR8-NEXT: iselgt r3, r4, r30 +; CHECK-PWR8-NEXT: li r4, 64 +; CHECK-PWR8-NEXT: ld r30, 80(r1) # 8-byte Folded Reload +; CHECK-PWR8-NEXT: lvx v31, r1, r4 # 16-byte Folded Reload +; CHECK-PWR8-NEXT: li r4, 48 +; CHECK-PWR8-NEXT: lvx v30, r1, r4 # 16-byte Folded Reload +; CHECK-PWR8-NEXT: addi r1, r1, 96 +; CHECK-PWR8-NEXT: ld r0, 16(r1) +; CHECK-PWR8-NEXT: mtlr r0 +; CHECK-PWR8-NEXT: blr %t1 = fcmp nnan ogt fp128 %a, %b %t2 = fcmp nnan olt fp128 %a, %b %t3 = sext i1 %t2 to i64 %t4 = select i1 %t1, i64 1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbf128: -; CHECK-NOT: li -; CHECK: xscmpuqp cr0, v2, v3 -; CHECK-NEXT: setb r3, cr0 -; CHECK-NOT: isel -; CHECK-NOT: li -; CHECK: blr -; CHECK-PWR8-LABEL: setbf128 -; CHECK-PWR8: isel -; CHECK-PWR8: blr } ; Some cases we can't leverage setb define i64 @setbn1(i64 %a, i64 %b) { +; CHECK-LABEL: setbn1: +; CHECK: # %bb.0: +; CHECK-NEXT: xor r5, r3, r4 +; CHECK-NEXT: cmpd r3, r4 +; CHECK-NEXT: li r3, -1 +; CHECK-NEXT: cntlzd r5, r5 +; CHECK-NEXT: rldicl r5, r5, 58, 63 +; CHECK-NEXT: isellt r3, r3, r5 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbn1: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: xor r6, r3, r4 +; CHECK-PWR8-NEXT: li r5, -1 +; CHECK-PWR8-NEXT: cntlzd r6, r6 +; CHECK-PWR8-NEXT: cmpd r3, r4 +; CHECK-PWR8-NEXT: rldicl r3, r6, 58, 63 +; CHECK-PWR8-NEXT: isellt r3, r5, r3 +; CHECK-PWR8-NEXT: blr %t1 = icmp slt i64 %a, %b %t2 = icmp eq i64 %a, %b %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbn1: -; CHECK-NOT: {{\<setb\>}} -; CHECK: isel -; CHECK: blr } define i64 @setbn2(double %a, double %b) { +; CHECK-LABEL: setbn2: +; CHECK: # %bb.0: +; CHECK-NEXT: fcmpu cr0, f1, f2 +; CHECK-NEXT: li r3, 1 +; CHECK-NEXT: li r4, -1 +; CHECK-NEXT: cror 4*cr5+lt, un, eq +; CHECK-NEXT: xscmpudp cr0, f1, f2 +; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt +; CHECK-NEXT: isellt r3, r4, r3 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbn2: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: fcmpu cr0, f1, f2 +; CHECK-PWR8-NEXT: xscmpudp cr1, f1, f2 +; CHECK-PWR8-NEXT: li r3, 1 +; CHECK-PWR8-NEXT: li r4, -1 +; CHECK-PWR8-NEXT: cror 4*cr5+lt, un, eq +; CHECK-PWR8-NEXT: isel r3, 0, r3, 4*cr5+lt +; CHECK-PWR8-NEXT: isel r3, r4, r3, 4*cr1+lt +; CHECK-PWR8-NEXT: blr %t1 = fcmp olt double %a, %b %t2 = fcmp one double %a, %b %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbn2: -; CHECK-NOT: {{\<setb\>}} -; CHECK: isel -; CHECK: blr } define i64 @setbn3(float %a, float %b) { +; CHECK-LABEL: setbn3: +; CHECK: # %bb.0: +; CHECK-NEXT: fcmpu cr0, f1, f2 +; CHECK-NEXT: li r3, 1 +; CHECK-NEXT: li r4, -1 +; CHECK-NEXT: iseleq r3, 0, r3 +; CHECK-NEXT: cror 4*cr5+lt, lt, un +; CHECK-NEXT: isel r3, r4, r3, 4*cr5+lt +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbn3: +; CHECK-PWR8: # %bb.0: +; CHECK-PWR8-NEXT: fcmpu cr0, f1, f2 +; CHECK-PWR8-NEXT: li r3, 1 +; CHECK-PWR8-NEXT: li r4, -1 +; CHECK-PWR8-NEXT: cror 4*cr5+lt, lt, un +; CHECK-PWR8-NEXT: iseleq r3, 0, r3 +; CHECK-PWR8-NEXT: isel r3, r4, r3, 4*cr5+lt +; CHECK-PWR8-NEXT: blr %t1 = fcmp ult float %a, %b %t2 = fcmp une float %a, %b %t3 = zext i1 %t2 to i64 %t4 = select i1 %t1, i64 -1, i64 %t3 ret i64 %t4 -; CHECK-LABEL: setbn3: -; CHECK-NOT: {{\<setb\>}} -; CHECK: isel -; CHECK: blr } ; Verify this case doesn't crash define void @setbn4(i128 %0, i32* %sel.out) { -entry: ; CHECK-LABEL: setbn4: -; CHECK-NOT: {{\<setb\>}} -; CHECK: isel -; CHECK: blr +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: li r6, 1 +; CHECK-NEXT: cmpdi cr1, r3, 0 +; CHECK-NEXT: li r3, 1 +; CHECK-NEXT: rldic r6, r6, 48, 15 +; CHECK-NEXT: cmpld r4, r6 +; CHECK-NEXT: crandc 4*cr5+lt, gt, eq +; CHECK-NEXT: crandc 4*cr5+gt, eq, 4*cr1+eq +; CHECK-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt +; CHECK-NEXT: rldicl. r4, r4, 16, 48 +; CHECK-NEXT: li r4, -1 +; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt +; CHECK-NEXT: iseleq r3, r4, r3 +; CHECK-NEXT: stw r3, 0(r5) +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: setbn4: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: li r6, 1 +; CHECK-PWR8-NEXT: cmpdi cr1, r3, 0 +; CHECK-PWR8-NEXT: li r3, 1 +; CHECK-PWR8-NEXT: rldic r6, r6, 48, 15 +; CHECK-PWR8-NEXT: cmpld r4, r6 +; CHECK-PWR8-NEXT: crandc 4*cr5+lt, gt, eq +; CHECK-PWR8-NEXT: crandc 4*cr5+gt, eq, 4*cr1+eq +; CHECK-PWR8-NEXT: rldicl. r4, r4, 16, 48 +; CHECK-PWR8-NEXT: li r4, -1 +; CHECK-PWR8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt +; CHECK-PWR8-NEXT: isel r3, 0, r3, 4*cr5+lt +; CHECK-PWR8-NEXT: iseleq r3, r4, r3 +; CHECK-PWR8-NEXT: stw r3, 0(r5) +; CHECK-PWR8-NEXT: blr +entry: %c1 = icmp ult i128 %0, 5192296858534827628530496329220096 %c2 = icmp ugt i128 %0, 5192296858534827628530496329220096 %ext = zext i1 %c2 to i32 diff --git a/llvm/test/CodeGen/PowerPC/store_fptoi.ll b/llvm/test/CodeGen/PowerPC/store_fptoi.ll index 737ead9946f1..dc534c2af171 100644 --- a/llvm/test/CodeGen/PowerPC/store_fptoi.ll +++ b/llvm/test/CodeGen/PowerPC/store_fptoi.ll @@ -26,11 +26,8 @@ define void @qpConv2sdw(fp128* nocapture readonly %a, i64* nocapture %b) { ; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std 0, 16(1) ; CHECK-PWR8-NEXT: stdu 1, -48(1) -; CHECK-PWR8-NEXT: ld 5, 0(3) -; CHECK-PWR8-NEXT: ld 6, 8(3) +; CHECK-PWR8-NEXT: lvx 2, 0, 3 ; CHECK-PWR8-NEXT: mr 30, 4 -; CHECK-PWR8-NEXT: mr 3, 5 -; CHECK-PWR8-NEXT: mr 4, 6 ; CHECK-PWR8-NEXT: bl __fixkfdi ; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: std 3, 0(30) @@ -66,11 +63,8 @@ define void @qpConv2sw(fp128* nocapture readonly %a, i32* nocapture %b) { ; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std 0, 16(1) ; CHECK-PWR8-NEXT: stdu 1, -48(1) -; CHECK-PWR8-NEXT: ld 5, 0(3) -; CHECK-PWR8-NEXT: ld 6, 8(3) +; CHECK-PWR8-NEXT: lvx 2, 0, 3 ; CHECK-PWR8-NEXT: mr 30, 4 -; CHECK-PWR8-NEXT: mr 3, 5 -; CHECK-PWR8-NEXT: mr 4, 6 ; CHECK-PWR8-NEXT: bl __fixkfsi ; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: stw 3, 0(30) @@ -106,11 +100,8 @@ define void @qpConv2udw(fp128* nocapture readonly %a, i64* nocapture %b) { ; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std 0, 16(1) ; CHECK-PWR8-NEXT: stdu 1, -48(1) -; CHECK-PWR8-NEXT: ld 5, 0(3) -; CHECK-PWR8-NEXT: ld 6, 8(3) +; CHECK-PWR8-NEXT: lvx 2, 0, 3 ; CHECK-PWR8-NEXT: mr 30, 4 -; CHECK-PWR8-NEXT: mr 3, 5 -; CHECK-PWR8-NEXT: mr 4, 6 ; CHECK-PWR8-NEXT: bl __fixunskfdi ; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: std 3, 0(30) @@ -146,11 +137,8 @@ define void @qpConv2uw(fp128* nocapture readonly %a, i32* nocapture %b) { ; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std 0, 16(1) ; CHECK-PWR8-NEXT: stdu 1, -48(1) -; CHECK-PWR8-NEXT: ld 5, 0(3) -; CHECK-PWR8-NEXT: ld 6, 8(3) +; CHECK-PWR8-NEXT: lvx 2, 0, 3 ; CHECK-PWR8-NEXT: mr 30, 4 -; CHECK-PWR8-NEXT: mr 3, 5 -; CHECK-PWR8-NEXT: mr 4, 6 ; CHECK-PWR8-NEXT: bl __fixunskfsi ; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: stw 3, 0(30) |