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path: root/include/opcode
Commit message (Expand)AuthorAgeFilesLines
* Limit moxie sto/ldo offsets to 16 bitsAnthony Green2014-12-272-4/+9
* Add Visium support to opcodesEric Botcazou2014-12-062-0/+341
* Remove broken nios2 assembler dwim support.Sandra Loosemore2014-11-282-6/+7
* Support ARM Cortex-M7Terry Guo2014-11-211-2/+7
* Add mach parameter to nios2_find_opcode_hash.Sandra Loosemore2014-11-062-3/+8
* MIPS: Add Octeon 3 supportNaveen H.S2014-10-311-0/+5
* Refactoring/cleanup of nios2 opcodes and assembler code.Sandra Loosemore2014-10-233-388/+551
* opcodes, elf: annotate instructions with HWCAP2_VIS3B.Jose E. Marchesi2014-10-172-1/+5
* This is a series of patches that add support for the SPARC M7 cpu toJose E. Marchesi2014-10-092-1/+39
* NDS32/opcodes: Add audio ISA extension and modify the disassemble implemnt.Kuan-Lin Chen2014-09-162-4/+10
* Add support for MIPS R6.Andrew Bennett2014-09-152-8/+113
* [PATCH/AArch64] Implement LSE featureJiong Wang2014-09-032-2/+15
* MIPS: Make the CODE10 operand code consistent between ISAsMaciej W. Rozycki2014-08-262-3/+9
* [MIPS] Rename COPROC related macrosMatthew Fortune2014-07-292-4/+11
* Add support for the AVR Tiny series of microcontrollers.Barney Stratford2014-07-012-17/+37
* Fix MSP430 assembler to support #hi(<symbol>).Nick Clifton2014-05-202-1/+6
* Add MIPS r3 and r5 support.Andrew Bennett2014-05-072-9/+54
* include/opcode/Richard Sandiford2014-05-012-10/+31
* Add support for the MIPS eXtended Physical Address (XPA) ASE.Andrew Bennett2014-04-231-0/+2
* Remove support for the (deprecated) openrisc and or32 configurations and replaceChristian Svensson2014-04-222-181/+4
* Update copyright yearsAlan Modra2014-03-0565-86/+69
* Range of element index is too large on MIPS MSA element selection instructions.Andrew Bennett2013-12-162-8/+13
* Add support for Andes NDS32:Kuan-Lin Chen2013-12-132-0/+834
* strip off +x bits on non-executable/script filesMike Frysinger2013-12-072-0/+4
* gas/testsuite/Yufeng Zhang2013-11-202-1/+6
* Add support for armv7ve to gas.Yufeng Zhang2013-11-182-5/+9
* Revert "Add support for AArch64 trace unit registers."Yufeng Zhang2013-11-182-2/+9
* gas/Yufeng Zhang2013-11-152-0/+7
* 2013-11-11 Catherine Moore <clm@codesourcery.com>Catherine Moore2013-11-111-2/+2
* gas/Yufeng Zhang2013-11-052-1/+16
* gas/Yufeng Zhang2013-11-052-0/+7
* 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu2013-10-142-7/+89
* * Removed short_hand field from opcode table andSean Keys2013-10-111-36/+16
* PR binutils/15834Nick Clifton2013-08-232-3/+8
* include/opcode/Richard Sandiford2013-08-192-4/+6
* include/opcode/Richard Sandiford2013-08-192-2/+4
* include/opcode/Richard Sandiford2013-08-192-0/+18
* gas/Eric Botcazou2013-08-051-0/+1
* include/opcode/Richard Sandiford2013-08-042-6/+59
* include/opcode/Richard Sandiford2013-08-032-11/+30
* include/opcode/Richard Sandiford2013-08-012-121/+88
* include/opcode/Richard Sandiford2013-08-012-10/+6
* Support Intel MPXH.J. Lu2013-07-242-0/+7
* include/opcode/Richard Sandiford2013-07-142-0/+14
* include/opcode/Richard Sandiford2013-07-142-0/+298
* include/opcode/Richard Sandiford2013-07-142-0/+6
* include/opcode/Richard Sandiford2013-07-072-90/+28
* include/opcode/Richard Sandiford2013-07-072-10/+13
* include/opcode/Richard Sandiford2013-07-072-5/+8
* include/opcode/Richard Sandiford2013-07-072-3/+10