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* Automatic date update in version.inGDB Administrator2023-07-091-1/+1
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* Automatic date update in version.inGDB Administrator2023-07-081-1/+1
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* Replace local variable called 'rename' with 'renamed'Nick Clifton2023-07-071-2/+2
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* Udated Freach and Romainian translations for various sub-directoriesNick Clifton2023-07-076-10572/+12318
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* ld: fix plugin tests for MIPS PICYunQiang Su2023-07-0710-0/+10
| | | | | | | | On MIPS, for PIC objects, symbols may reference 2 times: once from the caller, and once from GOT. Thus ld may complains 2 times about "undefined reference". So we add a new "#?" line to every effected testsuite.
* Automatic date update in version.inGDB Administrator2023-07-071-1/+1
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* Automatic date update in version.inGDB Administrator2023-07-061-1/+1
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* Automatic date update in version.inGDB Administrator2023-07-051-1/+1
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* Updated Ukranian, Romanian and German translations for various sub-directoriesNick Clifton2023-07-049-11349/+12933
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* Automatic date update in version.inGDB Administrator2023-07-041-1/+1
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* Change version number to 2.40.90 and regenerate filesNick Clifton2023-07-0323-8701/+9499
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* Add markers for the 2.41 branchNick Clifton2023-07-0316-0/+55
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* gas: NEWS: Announce LoongArch changes in the 2.41 cycleWANG Xuerui2023-07-031-0/+12
| | | | | | | | gas/ChangeLog: * NEWS: Mention LoongArch changes for 2.41. Signed-off-by: WANG Xuerui <git@xen0n.name>
* binutils: NEWS: Announce LoongArch changes in the 2.41 cycleWANG Xuerui2023-07-031-0/+14
| | | | | | | | binutils/ChangeLog: * NEWS: Mention LoongArch changes for 2.41. Signed-off-by: WANG Xuerui <git@xen0n.name>
* LoongArch: gas: Fix shared buildsWANG Xuerui2023-07-031-1/+0
| | | | | | | | | | | | | | | | | | Formerly an include of libbfd.h was added in commit 56576f4a722 ("LoongArch: gas: Add support for linker relaxation."), in order to allow calling _bfd_read_unsigned_leb128 from gas, but doing so broke shared builds. Commit d2fddb6d783 fixed this reference but did not remove the now unnecessary inclusion of libbfd.h. The gas_assert macro expands into a conditional call to abort(), but "abort" is re-defined to _bfd_abort in libbfd.h, so the extra include breaks any gas_assert usage, and should be removed. gas/ChangeLog: * config/tc-loongarch.c: Don't include libbfd.h. Fixes: d2fddb6d783 ("LoongArch: Fix ld "undefined reference" error with --enable-shared") Signed-off-by: WANG Xuerui <git@xen0n.name>
* opcodes/loongarch: Mark address offset operands of LVZ/LBT insns as suchWANG Xuerui2023-07-031-28/+28
| | | | | | | | | opcodes/ChangeLog: * loongarch-opc.c: Mark the offset operands as "so" for {,x}v{ld,st}, {,x}v{ldrepl,stelm}.[bhwd], and {ld,st}[lr].[wd]. Signed-off-by: WANG Xuerui <git@xen0n.name>
* Automatic date update in version.inGDB Administrator2023-07-031-1/+1
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* Automatic date update in version.inGDB Administrator2023-07-021-1/+1
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* gprofng: fix data raceVladimir Mezentsev2023-07-015-93/+34
| | | | | | | | | | | | | | | In our GUI project (https://savannah.gnu.org/projects/gprofng-gui), we use the output of gprofng to display the data. Sometimes this data is corrupted. gprofng/ChangeLog 2023-06-29 Vladimir Mezentsev <vladimir.mezentsev@oracle.com> * src/ipc.cc (ipc_doWork): Fix data race. * src/ipcio.cc (IPCresponse::print): Fix data race. Remove unused variables and functions. * src/ipcio.h: Declare two variables. * src/StringBuilder.cc (StringBuilder::write): New function. * src/StringBuilder.h: Likewise.
* binutils: NEWS: Announce new RISC-V vector crypto extensionsChristoph Müllner2023-07-011-0/+2
| | | | | | | | | | | This commit adds the recently added support of the RISC-V vector crypto extensions to the NEWS file. binutils/ChangeLog: * NEWS: Announce new RISC-V vector crypto extensions. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add support for the Zvksc ISA extensionNathan Huckleberry2023-07-013-0/+31
| | | | | | | | | | | | | | | | | | | | Zvksc is part of the vector crypto extensions. Zvksc is shorthand for the following set of extensions: - Zvks - Zvbc bfd/ChangeLog: * elfxx-riscv.c: Define Zvksc extension. gas/ChangeLog: * testsuite/gas/riscv/zvksc.d: New test. * testsuite/gas/riscv/zvksc.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add support for the Zvknc ISA extensionNathan Huckleberry2023-07-013-0/+31
| | | | | | | | | | | | | | | | | | | | Zvknc is part of the vector crypto extensions. Zvknc is shorthand for the following set of extensxions: - Zvkn - Zvbc bfd/ChangeLog: * elfxx-riscv.c: Define Zvknc extension. gas/ChangeLog: * testsuite/gas/riscv/zvknc.d: New test. * testsuite/gas/riscv/zvknc.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add support for the Zvksg ISA extensionNathan Huckleberry2023-07-013-0/+19
| | | | | | | | | | | | | | | | | | | | Zvksg is part of the vector crypto extensions. Zvksg is shorthand for the following set of extensions: - Zvks - Zvkg bfd/ChangeLog: * elfxx-riscv.c: Define Zvksg extension. gas/ChangeLog: * testsuite/gas/riscv/zvksg.d: New test. * testsuite/gas/riscv/zvksg.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add support for the Zvks ISA extensionChristoph Müllner2023-07-013-0/+85
| | | | | | | | | | | | | | | | | | | | | | Zvks is part of the vector crypto extensions. Zvks is shorthand for the following set of extensions: - Zvksed - Zvksh - Zvbb - Zvkt bfd/ChangeLog: * elfxx-riscv.c: Define Zvks extension. gas/ChangeLog: * testsuite/gas/riscv/zvks.d: New test. * testsuite/gas/riscv/zvks.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add support for the Zvkng ISA extensionNathan Huckleberry2023-07-013-0/+19
| | | | | | | | | | | | | | | | | | | | Zvkng is part of the vector crypto extensions. Zvkng is shorthand for the following set of extensions: - Zvkn - Zvkg bfd/ChangeLog: * elfxx-riscv.c: Define Zvkng extension. gas/ChangeLog: * testsuite/gas/riscv/zvkng.d: New test. * testsuite/gas/riscv/zvkng.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Allow nested implications for extensionsNathan Huckleberry2023-07-011-7/+22
| | | | | | | | | | | | | | | | Certain extensions require two levels of implications. For example, zvkng implies zvkn and zvkn implies zvkned. Enabling zvkng should also enable zvkned. This patch fixes this behavior. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_add_implicit_subsets): Allow nested implications for extensions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add support for the Zvkn ISA extensionChristoph Müllner2023-07-013-0/+86
| | | | | | | | | | | | | | | | | | | | | | Zvkn is part of the vector crypto extensions. Zvkn is shorthand for the following set of extensions: - Zvkned - Zvknhb - Zvbb - Zvkt bfd/ChangeLog: * elfxx-riscv.c: Define Zvkn extension. gas/ChangeLog: * testsuite/gas/riscv/zvkn.d: New test. * testsuite/gas/riscv/zvkn.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add support for the Zvksh ISA extensionChristoph Müllner2023-07-016-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zvksh is part of the vector crypto extensions. This extension adds the following instructions: - vsm3me.vv - vsm3c.vi bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvksh. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvksh.d: New test. * testsuite/gas/riscv/zvksh.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSM3C_VI): New. (MASK_VSM3C_VI): New. (MATCH_VSM3ME_VV): New. (MASK_VSM3ME_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvksh. opcodes/ChangeLog: * riscv-opc.c: Add Zvksh instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add support for the Zvksed ISA extensionChristoph Müllner2023-07-016-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zvksed is part of the vector crypto extensions. This extension adds the following instructions: - vsm4k.vi - vsm4r.[vv,vs] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvksed. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvksed.d: New test. * testsuite/gas/riscv/zvksed.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSM4K_VI): New. (MASK_VSM4K_VI): New. (MATCH_VSM4R_VS): New. (MASK_VSM4R_VS): New. (MATCH_VSM4R_VV): New. (MASK_VSM4R_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvksed. opcodes/ChangeLog: * riscv-opc.c: Add Zvksed instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add support for the Zvknh[a,b] ISA extensionsChristoph Müllner2023-07-017-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zvknh[a,b] are parts of the vector crypto extensions. This extension adds the following instructions: - vsha2ms.vv - vsha2c[hl].vv bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvknh[a,b]. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvknha.d: New test. * testsuite/gas/riscv/zvknha_zvknhb.s: New test. * testsuite/gas/riscv/zvknhb.d: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSHA2CH_VV): New. (MASK_VSHA2CH_VV): New. (MATCH_VSHA2CL_VV): New. (MASK_VSHA2CL_VV): New. (MATCH_VSHA2MS_VV): New. (MASK_VSHA2MS_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvknh[a,b]. opcodes/ChangeLog: * riscv-opc.c: Add Zvknh[a,b] instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add support for the Zvkned ISA extensionChristoph Müllner2023-07-016-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zvkned is part of the vector crypto extensions. This extension adds the following instructions: - vaesef.[vv,vs] - vaesem.[vv,vs] - vaesdf.[vv,vs] - vaesdm.[vv,vs] - vaeskf1.vi - vaeskf2.vi - vaesz.vs bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvkned. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvkned.d: New test. * testsuite/gas/riscv/zvkned.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VAESDF_VS): New. (MASK_VAESDF_VS): New. (MATCH_VAESDF_VV): New. (MASK_VAESDF_VV): New. (MATCH_VAESDM_VS): New. (MASK_VAESDM_VS): New. (MATCH_VAESDM_VV): New. (MASK_VAESDM_VV): New. (MATCH_VAESEF_VS): New. (MASK_VAESEF_VS): New. (MATCH_VAESEF_VV): New. (MASK_VAESEF_VV): New. (MATCH_VAESEM_VS): New. (MASK_VAESEM_VS): New. (MATCH_VAESEM_VV): New. (MASK_VAESEM_VV): New. (MATCH_VAESKF1_VI): New. (MASK_VAESKF1_VI): New. (MATCH_VAESKF2_VI): New. (MASK_VAESKF2_VI): New. (MATCH_VAESZ_VS): New. (MASK_VAESZ_VS): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvkned. opcodes/ChangeLog: * riscv-opc.c: Add Zvkned instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add support for the Zvkg ISA extensionChristoph Müllner2023-07-016-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zvkg is part of the vector crypto extensions. This extension adds the following instructions: - vghsh.vv - vgmul.vv bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvkg. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvkg.d: New test. * testsuite/gas/riscv/zvkg.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VGHSH_VV): New. (MASK_VGHSH_VV): New. (MATCH_VGMUL_VV): New. (MASK_VGMUL_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvkg. opcodes/ChangeLog: * riscv-opc.c: Add Zvkg instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add support for the Zvbc extensionNathan Huckleberry2023-07-016-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zvbc is part of the crypto vector extensions. This extension adds the following instructions: - vclmul.[vv,vx] - vclmulh.[vv,vx] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvbc. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvbc.d: New test. * testsuite/gas/riscv/zvbc.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VCLMUL_VV): New. (MASK_VCLMUL_VV): New. (MATCH_VCLMUL_VX): New. (MASK_VCLMUL_VX): New. (MATCH_VCLMULH_VV): New. (MASK_VCLMULH_VV): New. (MATCH_VCLMULH_VX): New. (MASK_VCLMULH_VX): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvbc. opcodes/ChangeLog: * riscv-opc.c: Add Zvbc instruction. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add support for the Zvbb ISA extensionChristoph Müllner2023-07-018-0/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zvbb is part of the vector crypto extensions. This extension adds the following instructions: - vandn.[vv,vx] - vbrev.v - vbrev8.v - vrev8.v - vclz.v - vctz.v - vcpop.v - vrol.[vv,vx] - vror.[vv,vx,vi] - vwsll.[vv,vx,vi] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvbb. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add 'l' as new format string directive. (riscv_ip): Likewise. * testsuite/gas/riscv/zvbb.d: New test. * testsuite/gas/riscv/zvbb.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VANDN_VV): New. (MASK_VANDN_VV): New. (MATCH_VANDN_VX): New. (MASK_VANDN_VX): New. (MATCH_VBREV8_V): New. (MASK_VBREV8_V): New. (MATCH_VBREV_V): New. (MASK_VBREV_V): New. (MATCH_VCLZ_V): New. (MASK_VCLZ_V): New. (MATCH_VCPOP_V): New. (MASK_VCPOP_V): New. (MATCH_VCTZ_V): New. (MASK_VCTZ_V): New. (MATCH_VREV8_V): New. (MASK_VREV8_V): New. (MATCH_VROL_VV): New. (MASK_VROL_VV): New. (MATCH_VROL_VX): New. (MASK_VROL_VX): New. (MATCH_VROR_VI): New. (MASK_VROR_VI): New. (MATCH_VROR_VV): New. (MASK_VROR_VV): New. (MATCH_VROR_VX): New. (MASK_VROR_VX): New. (MATCH_VWSLL_VI): New. (MASK_VWSLL_VI): New. (MATCH_VWSLL_VV): New. (MASK_VWSLL_VV): New. (MATCH_VWSLL_VX): New. (MASK_VWSLL_VX): New. (DECLARE_INSN): New. * opcode/riscv.h (EXTRACT_RVV_VI_UIMM6): New. (ENCODE_RVV_VI_UIMM6): New. (enum riscv_insn_class): Add instruction class for Zvbb. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add 'l' as new format string directive. * riscv-opc.c: Add Zvbb instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* Automatic date update in version.inGDB Administrator2023-07-011-1/+1
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* Fix regressions caused by agent expression C++-ificationTom Tromey2023-06-301-4/+4
| | | | | | | | | | Simon pointed out that my agent expression C++-ification patches caused a regression with the native-gdbserver target board. The bug is that append_const is supposed to write in big-endian order, but I switched this by mistake.
* binutils: NEWS: announce new RISC-V extensionsPhilipp Tomsich2023-06-301-0/+7
| | | | | | | | | | | | | We picked up support for a few new extensions over the last weeks (this may need further updating prior to the next release), list them in the NEWS file. binutils/ChangeLog: * binutils/NEWS: announce suuport for the new RISC-V extensions (Zicond, Zfa, XVentanaCondOps). Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
* RISC-V: Add support for the Zfa extensionChristoph Müllner2023-06-3016-0/+550
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the RISC-V Zfa extension, which introduces additional floating-point instructions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Modular Convert-to-Integer) * fmv* to access high bits of FP registers in case XLEN < FLEN * fleq/fltq (quiet comparison instructions) Zfa defines its instructions in combination with the following extensions: * single-precision floating-point (F) * double-precision floating-point (D) * quad-precision floating-point (Q) * half-precision floating-point (Zfh) This patch is based on an earlier version from Tsukasa OI: https://sourceware.org/pipermail/binutils/2022-September/122939.html Most significant change to that commit is the switch from the rs1-field value to the actual floating-point value in the last operand of the fli* instructions. Everything that strtof() can parse is accepted and the '%a' printf specifier is used to output hex floating-point literals in the disassembly. The Zfa specification is frozen (and has passed public review). It is available as a chapter in "The RISC-V Instruction Set Manual: Volume 1": https://github.com/riscv/riscv-isa-manual/releases bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for 'Zfa' extension. (riscv_multi_subset_supports_ext): Likewise. (riscv_implicit_subsets): Add 'Zfa' -> 'F' dependency. gas/ChangeLog: * config/tc-riscv.c (flt_lookup): New helper to lookup a float value in an array. (validate_riscv_insn): Add 'Wfv' as new format string directive. (riscv_ip): Likewise. * doc/c-riscv.texi: Add floating-point chapter and describe limiations of the Zfa FP literal parsing. * testsuite/gas/riscv/zfa-32.d: New test. * testsuite/gas/riscv/zfa-32.s: New test. * testsuite/gas/riscv/zfa-64.d: New test. * testsuite/gas/riscv/zfa-64.s: New test. * testsuite/gas/riscv/zfa-fail.d: New test. * testsuite/gas/riscv/zfa-fail.l: New test. * testsuite/gas/riscv/zfa-fail.s: New test. * testsuite/gas/riscv/zfa.d: New test. * testsuite/gas/riscv/zfa.s: New test. * testsuite/gas/riscv/zfa.s: New test. * opcode/riscv-opc.h (MATCH_FLI_H): New. (MASK_FLI_H): New. (MATCH_FMINM_H): New. (MASK_FMINM_H): New. (MATCH_FMAXM_H): New. (MASK_FMAXM_H): New. (MATCH_FROUND_H): New. (MASK_FROUND_H): New. (MATCH_FROUNDNX_H): New. (MASK_FROUNDNX_H): New. (MATCH_FLTQ_H): New. (MASK_FLTQ_H): New. (MATCH_FLEQ_H): New. (MASK_FLEQ_H): New. (MATCH_FLI_S): New. (MASK_FLI_S): New. (MATCH_FMINM_S): New. (MASK_FMINM_S): New. (MATCH_FMAXM_S): New. (MASK_FMAXM_S): New. (MATCH_FROUND_S): New. (MASK_FROUND_S): New. (MATCH_FROUNDNX_S): New. (MASK_FROUNDNX_S): New. (MATCH_FLTQ_S): New. (MASK_FLTQ_S): New. (MATCH_FLEQ_S): New. (MASK_FLEQ_S): New. (MATCH_FLI_D): New. (MASK_FLI_D): New. (MATCH_FMINM_D): New. (MASK_FMINM_D): New. (MATCH_FMAXM_D): New. (MASK_FMAXM_D): New. (MATCH_FROUND_D): New. (MASK_FROUND_D): New. (MATCH_FROUNDNX_D): New. (MASK_FROUNDNX_D): New. (MATCH_FLTQ_D): New. (MASK_FLTQ_D): New. (MATCH_FLEQ_D): New. (MASK_FLEQ_D): New. (MATCH_FLI_Q): New. (MASK_FLI_Q): New. (MATCH_FMINM_Q): New. (MASK_FMINM_Q): New. (MATCH_FMAXM_Q): New. (MASK_FMAXM_Q): New. (MATCH_FROUND_Q): New. (MASK_FROUND_Q): New. (MATCH_FROUNDNX_Q): New. (MASK_FROUNDNX_Q): New. (MATCH_FLTQ_Q): New. (MASK_FLTQ_Q): New. (MATCH_FLEQ_Q): New. (MASK_FLEQ_Q): New. (MATCH_FCVTMOD_W_D): New. (MASK_FCVTMOD_W_D): New. (MATCH_FMVH_X_D): New. (MASK_FMVH_X_D): New. (MATCH_FMVH_X_Q): New. (MASK_FMVH_X_Q): New. (MATCH_FMVP_D_X): New. (MASK_FMVP_D_X): New. (MATCH_FMVP_Q_X): New. (MASK_FMVP_Q_X): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction classes for the Zfa extension. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add support for new format string directive 'Wfv'. * riscv-opc.c: Add Zfa instructions. Co-Developed-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Co-Developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
* strings: Improve code to detect excessively large minimum string lengths.Nick Clifton2023-06-302-18/+37
| | | | | PR 30598 * strings.c (set_string_min): New function. (main): Use it. (print_unicode_stream): Calculate buffer size using a size_t.
* Prevent an illegal memory access when running the strings program with an ↵Nick Clifton2023-06-302-0/+12
| | | | | | | excessively lerge minimum string length. PR 30595 * strings.c (main): Check for an excessively large minimum string length.
* Fix used-before-initialized warnings when compiling elf.c with Clang-16.Nick Clifton2023-06-301-2/+4
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* LoongArch: gas: Fix code style issuesmengqinggang2023-06-301-1682/+1681
| | | | | Blocks of 8 spaces be replaced with tabs. Fix alignment issues.
* LoongArch: gas: Add LVZ and LBT instructions supportmengqinggang2023-06-307-28/+608
| | | | | | | | | | | | | | | | | | gas/ChangeLog: * config/tc-loongarch.c (md_parse_option): Add LARCH_opts.ase_lvz and LARCH_opts.ase_lbt. * testsuite/gas/loongarch/uleb128.d: Regenerated. * testsuite/gas/loongarch/lvz-lbt.d: New test. * testsuite/gas/loongarch/lvz-lbt.s: New test. include/ChangeLog: * opcode/loongarch.h (ase_lvz): New. (ase_lbt): New. opcodes/ChangeLog: * loongarch-dis.c (set_default_loongarch_dis_options): Add LARCH_opts.ase_lvz and LARCH_opts.ase_lbt. * loongarch-opc.c (struct loongarch_ase): Add LVZ and LBT instructions.
* LoongArch: Deprecate $v[01], $fv[01] and $x names per specWANG Xuerui2023-06-306-11/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As outlined in the LoongArch ELF psABI spec [1], it is actually already 2 versions after the initial LoongArch support, and the $v[01] and $fv[01] names should really get sunset by now. In addition, the "$x" name for $r21 was never included in any released version of the ABI spec, and such usages are all fixed to say just $r21 for every project I could think of that accepted a LoongArch port. Plus, the upcoming LSX/LASX support makes use of registers named "$vrNN" and "$xrNN", so having "$vN" and "$x" alongside would almost certainly create confusion for developers. Issue warnings for such usages per the deprecation procedure detailed in the spec, so we can finally remove support in the next release cycle after this. [1]: https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html gas/ChangeLog: * config/tc-loongarch.c: Init canonical register ABI name mappings and deprecated register names. (loongarch_args_parser_can_match_arg_helper): Warn in case of deprecated register name usage. * testsuite/gas/loongarch/deprecated_reg_aliases.d: New test. * testsuite/gas/loongarch/deprecated_reg_aliases.l: Likewise. * testsuite/gas/loongarch/deprecated_reg_aliases.s: Likewise. include/ChangeLog: * opcode/loongarch.h: Rename global variables. opcodes/ChangeLog: * loongarch-opc.c: Rename the alternate/deprecated register name mappings, and move $x to the deprecated name map. Signed-off-by: WANG Xuerui <git@xen0n.name>
* opcodes/loongarch: print unrecognized insn words with the .word directiveWANG Xuerui2023-06-304-10/+29
| | | | | | | | | | | | | | | | For better round-trip fidelity and readability in general. gas/ChangeLog: * testsuite/gas/loongarch/uleb128.d: Update test case. * testsuite/gas/loongarch/raw-insn.d: New test. * testsuite/gas/loongarch/raw-insn.s: Likewise. opcodes/ChangeLog: * loongarch-dis.c (disassemble_one): Print ".word" if !opc. Signed-off-by: WANG Xuerui <git@xen0n.name>
* opcodes/loongarch: do not print hex notation for signed immediatesWANG Xuerui2023-06-3014-257/+251
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The additional hex notation was minimally useful when one had to inspect code with heavy bit manipulation, or of unclear signedness, but it clutters the output, and the style is not regular assembly language syntax either. Precisely how one approaches the original use case is not taken care of in this patch (maybe we want a disassembler option forcing a certain style for immediates, like for example printing every immediate in decimal or hexadecimal notation), but at least let's stop the current practice. ChangeLog: * testsuite/gas/loongarch/imm_ins.d: Update test case. * testsuite/gas/loongarch/imm_ins_32.d: Likewise. * testsuite/gas/loongarch/imm_op.d: Likewise. * testsuite/gas/loongarch/jmp_op.d: Likewise. * testsuite/gas/loongarch/load_store_op.d: Likewise. * testsuite/gas/loongarch/macro_op.d: Likewise. * testsuite/gas/loongarch/macro_op_32.d: Likewise. * testsuite/gas/loongarch/privilege_op.d: Likewise. * testsuite/gas/loongarch/uleb128.d: Likewise. * testsuite/gas/loongarch/vector.d: Likewise. ld/ChangeLog: * testsuite/ld-loongarch-elf/jmp_op.d: Update test case. * testsuite/ld-loongarch-elf/macro_op.d: Likewise. * testsuite/ld-loongarch-elf/macro_op_32.d: Likewise. opcodes/ChangeLog: * loongarch-dis.c (dis_one_arg): Remove the "(0x%x)" part from disassembly output of signed immediate operands. Signed-off-by: WANG Xuerui <git@xen0n.name>
* opcodes/loongarch: style disassembled address offsets as suchWANG Xuerui2023-06-302-28/+41
| | | | | | | | | | | | | | | Add a modifier char 'o' telling the disassembler to print the immediate using the address offset style, and mark the memory access instructions' offset operands as such. opcodes/ChangeLog: * loongarch-dis.c (dis_one_arg): Style disassembled address offsets as such when the operand has a modifier char 'o'. * loongarch-opc.c: Add 'o' to operands that represent address offsets. Signed-off-by: WANG Xuerui <git@xen0n.name>
* opcodes/loongarch: implement style support in the disassemblerWANG Xuerui2023-06-302-23/+27
| | | | | | | | | | | | | Update the LoongArch disassembler to supply style information to the disassembler output. The output formatting remains unchanged. opcodes/ChangeLog: * disassemble.c: Mark LoongArch as created_styled_output=true. * loongarch-dis.c (dis_one_arg): Use fprintf_styled_func throughout with proper styles. Signed-off-by: WANG Xuerui <git@xen0n.name>
* opcodes/loongarch: remove unused codeWANG Xuerui2023-06-302-40/+0
| | | | | | | | | | | | | | | | Remove some unused declarations and code. include/ChangeLog: * opcode/loongarch.h: Remove unused declarations. opcodes/ChangeLog: * loongarch-dis.c (loongarch_parse_dis_options): Remove. (my_print_address_func): Likewise. (loongarch_disassemble_one): Likewise. Signed-off-by: WANG Xuerui <git@xen0n.name>
* LoongArch: support disassembling certain pseudo-instructionsWANG Xuerui2023-06-3020-64/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a flag in the pinfo field for being able to mark certain specialized matchers as disassembler-only, so some degree of isolation between assembler-side and disassembler-side can be achieved. This isolation is necessary, firstly because some pseudo-instructions cannot be fully described in the opcode table, like `li.[wd]`, so the corresponding opcode entry cannot have meaningful match/mask values. Secondly, some of these pseudo-instructions can be realized in more than one plausible ways; e.g. `li.w rd, <something between 0 and 0x7ff>` can be realized on LA64 with any of `addi.w`, `addi.d` or `ori`. If we tie disassembly of such aliases with the corresponding GAS support, only one canonical form among the above would be recognized as `li.w`, and it would mildly impact the readability of disassembly output. People wanting the exact disassembly can always set `-M no-aliases` to get the original behavior back. In addition, in certain cases, information is irreversibly lost after assembling, so perfect round-trip would not be possible in such cases. For example, `li.w` and `li.d` of immediates within int32_t range produce the same code; in this patch, `addi.d rd, $zero, imm` is treated as `li.d`, while `addi.w` and `ori` immediate loads are shown as `li.w`, due to the expressible value range well within 32 bits. gas/ChangeLog: * config/tc-loongarch.c (get_loongarch_opcode): Ignore disassembler-only aliases. * testsuite/gas/loongarch/64_pcrel.d: Update test case. * testsuite/gas/loongarch/imm_ins.d: Likewise. * testsuite/gas/loongarch/imm_ins_32.d: Likewise. * testsuite/gas/loongarch/jmp_op.d: Likewise. * testsuite/gas/loongarch/li.d: Likewise. * testsuite/gas/loongarch/macro_op.d: Likewise. * testsuite/gas/loongarch/macro_op_32.d: Likewise. * testsuite/gas/loongarch/macro_op_large_abs.d: Likewise. * testsuite/gas/loongarch/macro_op_large_pc.d: Likewise. * testsuite/gas/loongarch/nop.d: Likewise. * testsuite/gas/loongarch/relax_align.d: Likewise. * testsuite/gas/loongarch/reloc.d: Likewise. include/ChangeLog: * opcode/loongarch.h (INSN_DIS_ALIAS): Add. ld/ChangeLog: * testsuite/ld-loongarch-elf/jmp_op.d: Update test case. * testsuite/ld-loongarch-elf/macro_op.d: Likewise. * testsuite/ld-loongarch-elf/macro_op_32.d: Likewise. * testsuite/ld-loongarch-elf/relax-align.dd: Likewise. opcodes/ChangeLog: * loongarch-dis.c: Move register name map declarations to top. (get_loongarch_opcode_by_binfmt): Consider aliases when disassembling without the no-aliases option. (parse_loongarch_dis_option): Support the no-aliases option. * loongarch-opc.c: Collect pseudo instructions into a new dedicated table. Signed-off-by: WANG Xuerui <git@xen0n.name>